Semiconductor device, method for designing the same and recording medium that can be read by computer in which program for designing semiconductor device is recorded

ABSTRACT

A semiconductor device of the present invention comprises a first semiconductor chip that includes a first internal circuit and at least one first conductive pad which is provided on its upper surface and is not connected to the first internal circuit, a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and at least one second conductive pad which is provided on its upper surface and is connected to the second internal circuit, at least one first connecting member for connecting between the second semiconductor chip provided on the first semiconductor chip, at least one first conductive pad and at least one second conductive pad, and at least one second connecting member led from at least one first conductive.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device that aplurality of semiconductor chips are integrally structured and inparticular to, facilitation of design for the semiconductor device.

[0002] A semiconductor device with a plurality of semiconductor chipsbeing integrally structured therein is conventionally designed so thatpads for the semiconductor chips are connected together by utilizingwire bonding connection or flip chip connection.

[0003] A conventional semiconductor device with a plurality ofsemiconductor chips being integrally structured therein will bedescribed hereinafter.

[0004]FIG. 27 is a view showing the structure of a conventionalsemiconductor device with a plurality of semiconductor chips beingintegrally structured therein. FIG. 28 is a cross-sectional view takenalong a line X-X shown in FIG. 27.

[0005] As shown in FIGS. 27 and 28, a semiconductor device 1000comprises a semiconductor chip B, a semiconductor chip A which isadhered on the semiconductor chip B with an adhered portion beinginterposed therebetween and wires 11, 12, 13, 14, 15, 16, 21, 22, 23,24, 25 and 26 extended from pads for the semiconductor chips A and B bywire bonding.

[0006] The wires 13, 15, 23 and 25 connect the pads for the chip A tothe pad for the chip B. The wires 12, 14, 22 and 24 connect the pads forthe chip A to electrodes outside the semiconductor device 1000 (e.g.,lead frame, electrode pad for printed wiring board and the like). Thewires 11, 16, 21 and 26 connect the pad for the chip B to external ofthe semiconductor device 1000.

[0007] There arise following various problems in designing andmanufacturing the conventional semiconductor device 1000.

[0008] Firstly, as shown in FIG. 28, in accordance with the conventionalsemiconductor device 1000, a maximum distance h from the wire 12 or 22to the upper surface of the semiconductor chip B is extremely long.Further, portions of the wires 12 and 22 that are not connected to padsare long. For this reason, the wires 12 and 22 are easily bent by anexternal stress. Consequently, when the wires are provided and then thesemiconductor device 1000 is to be worked, the wires 12 and 22 and thewires 11 and 21 may be shorted. As a result, yield rates for productsobtained by working the semiconductor device 1000 may be decreased.

[0009] Moreover, since the positions of the pads for the semiconductorchips A and B are fixed in the conventional semiconductor device 1000, adegree of freedom in wiring design is low.

[0010] In accordance with the conventional semiconductor device 1000,wires for connecting the semiconductor A to the semiconductor B (e.g.,the wires 12 and 14) may have different lengths. Thus, such wires mayhave various delay values.

[0011] The semiconductor chip B does not have marks for fixing thesemiconductor A thereon. Thus, when the conventional semiconductordevice 1000 is manufactured, it is difficult to adhere the semiconductorchip A on the semiconductor chip B so that the semiconductor chip A issecurely fixed on a predetermined position of the semiconductor chip B.

[0012] When the semiconductor chip A and other semiconductor chip withthe same size as the semiconductor chip A are adhered on thesemiconductor chip B, the semiconductor chip A may be mistaken for theother semiconductor chip.

[0013] The semiconductor chip A is provided with only pads for wirebonding. Thus, the semiconductor chip A is connected to thesemiconductor chip B only by wire bonding.

[0014] In accordance with the conventional semiconductor device 1000,since the space between the semiconductor chips A and B is not shieldedat a ground potential, EMI (Electro Magnetic Interference) may occurthereat.

SUMMARY OF THE INVENTION

[0015] The present invention was developed in light of theabove-described drawbacks and an object of the present invention is toprovide a semiconductor device which is easily designed and manufacturedand in which a plurality of semiconductor chips are integrallystructured.

[0016] A semiconductor device of the present invention comprises a firstsemiconductor chip that includes a first internal circuit and at leastone first conductive pad which is provided on its upper surface and isnot connected to the first internal circuit; a second semiconductor chipprovided on the first semiconductor chip that includes a second internalcircuit and at least one second conductive pad which is provided on itsupper surface and connected to the second internal circuit; at least onefirst connecting member for connecting the at least one first conductivepad to the at least one second conductive pad; and at least one secondconnecting member led from the at least one first conductive pad.

[0017] In accordance with the present invention, bent of connectingmembers occurred in a conventional semiconductor device can besuppressed. Accordingly, when the connecting members are provided andthen a semiconductor device is worked, short of the connecting memberscan be prevented.

[0018] The at least one first connecting member may contact the point onthe at least one first conductive pad which is different from the pointthe at least one second connecting member contacts.

[0019] Thus, it is possible to prevent the second connecting member ledfrom the first conductive pad from contacting other components. Namely,a degree of freedom in designing wiring is improved.

[0020] Preferably, a plurality of the at least one first conductive padsare provided, a plurality of the at least one second conductive pads areprovided, a plurality of the at least one first connecting member areprovided, a plurality of the at least one second connecting member areprovided, and two of the plurality of first connecting members have thesame length.

[0021] A skew generated because of the difference in length between thefirst connecting members can be reduced.

[0022] A semiconductor device of the present invention comprises a firstsemiconductor chip that includes a plurality of first conductive padsprovided on its upper surface; a second semiconductor chip that isprovided on the first semiconductor chip and includes a plurality ofsecond conductive pads provided on its upper surface; and a plurality offirst connecting members for connecting the plurality of firstconductive pads to the plurality of second conductive pads, wherein atleast one of the plurality of first connecting members has a resistancevalue per unit length different from those of the other first connectingmembers.

[0023] In accordance with the present invention, a delay value can beadjusted for each of the first connecting members.

[0024] At least one of the plurality of first connecting members may bemade of a material different from those of the other first connectingmembers.

[0025] The number of wires for at least one of the plurality of firstconnecting members may be different from those of the other firstconnecting members.

[0026] A semiconductor device of the present invention comprises a firstsemiconductor chip; and a second semiconductor chip provided on thefirst semiconductor chip, wherein fixing means for disposing the secondsemiconductor chip is provided on the first semiconductor chip.

[0027] In accordance with the present invention, a semiconductor devicethat a second semiconductor chip is securely fixed on a firstsemiconductor chip without misalignment can be obtained.

[0028] The fixing means may be a first convex portion with which thesecond semiconductor chip can engage.

[0029] Preferably, a second convex portion on which the secondsemiconductor chip can slide is formed at areas on the firstsemiconductor chip other than the area that the second semiconductorchip is to be disposed.

[0030] Even if the second semiconductor chip is disposed at areas otherthan the area that the second semiconductor chip should be originallydisposed when being fixed on the first semiconductor chip, the secondsemiconductor chip slides on the second convex portions and is fixed onthe area defined by the first convex portions.

[0031] A semiconductor device of the present invention comprises a firstsemiconductor chip; and a second semiconductor chip provided on thefirst semiconductor chip, wherein the first semiconductor chip has afirst engagement portion, the second semiconductor chip has a secondengagement portion, and the first engagement portion is fitted into thesecond engagement portion.

[0032] In accordance with the present invention, when being fixed on thefirst semiconductor chip, the second semiconductor chip is securelyfixed on the first semiconductor chip without misalignment.

[0033] The semiconductor device may further comprise a thirdsemiconductor chip provided on the first semiconductor chip, wherein thethird semiconductor chip has a third engagement portion, the firstsemiconductor chip has a fourth engagement portion, the third engagementis fitted into the fourth engagement portion and the first engagementportion has different configuration from the third engagement portion.

[0034] If the third semiconductor chip is mistaken for the secondsemiconductor chip, the second semiconductor chip and the thirdsemiconductor chip cannot be fixed on the first semiconductor chip.Thus, it is possible to prevent the second semiconductor chip frommistaken for the third semiconductor chip.

[0035] A semiconductor device of the present invention comprises a firstsemiconductor chip; and a second semiconductor chip provided on thefirst semiconductor chip, wherein a first mark indicating the area thesecond semiconductor chip is to be disposed is provided on the firstsemiconductor chip.

[0036] In accordance with the present invention, when the secondsemiconductor chip is fixed on the first semiconductor chip, it ispossible to prevent the second semiconductor from mistaken for othersemiconductor chips.

[0037] The semiconductor device may further comprise a thirdsemiconductor chip provided on the first semiconductor chip, wherein asecond mark indicating the area the third semiconductor chip is to bedisposed is provided on the first semiconductor chip, the first mark isdifferent from the second mark.

[0038] A semiconductor device of the present invention comprises aninternal circuit; a wire bonding conductive pad connected to theinternal circuit; and a bump connection pad connected to the internalcircuit in parallel with the wire bond conductive pad.

[0039] In accordance with the present invention, if desired, aconnection method for structuring a semiconductor device can beselected.

[0040] The semiconductor device may comprise a first surface; and asecond surface opposing the first surface, wherein the wire bondingconductive pad and the bump connection pad are provided on the firstsurface.

[0041] A semiconductor device of the present invention comprises a firstsemiconductor chip that includes a plurality of first conductive padsprovided on it upper surface; a second semiconductor chip provided onthe first semiconductor chip that includes a plurality of secondconductive pads provided on its upper surface; a plurality of firstconnecting members for connecting the plurality of first conductive padsto the plurality of second conductive pads; and a plurality of secondconnecting members led from the plurality of second conductive pads,with a ground potential beings supplied thereto.

[0042] In accordance with the present invention, as a plurality ofconnecting members are connected to a ground potential Vss, potentialsof the plurality of connecting members are all fixed to the groundpotential Vss. Thus, the space between the first semiconductor chip andthe second semiconductor chip is substantially electrically shielded,and EMI (Electro Magnetic Interference) can be suppressed and prevented.

[0043] In accordance with the present invention, a method for designingsemiconductor device which comprises a first semiconductor chip thatincludes a first internal circuit, a first conductive pad which isprovided on its upper surface and is connected to the first internalcircuit and a wire bond island serving as a conductive pad which isprovided on its upper surface and is not connected to the first internalcircuit; and a second semiconductor chip provided on the firstsemiconductor chip that includes a second internal circuit and a secondconductive pad which is provided on its upper surface and is connectedto the second internal circuit, wherein the first conductive pad isconnected to the second conductive pad, and the first conductive pad isconnected to externals, the method comprising the steps of: (a)determining a connection path which can be connected by wire bondingfrom the connection relationship between the internal circuits and theexternals and the positions of the conductive pads; and (b) calculating,with respect to the connection path, the position of the wire bondisland provided on the first semiconductor chip.

[0044] In accordance with the method for designing semiconductor deviceof the present invention, a semiconductor device that bent of connectingmembers occurred in a conventional semiconductor device is suppressedcan be obtained.

[0045] A method for designing semiconductor device which comprises afirst semiconductor chip that includes a first internal circuit, atleast one first conductive pad which is provided on its upper surfaceand is connected to the first internal circuit and at least one wirebond island serving as a conductive pad which is provided on its uppersurface and is not connected to the first internal circuit; and a secondsemiconductor chip provided on the first semiconductor chip thatincludes a second internal circuit and a second conductive pad which isprovided on its upper surface and is connected to the second internalcircuit, wherein the at least one first conductive pad is connected tothe second conductive pad, and the at least one first conductive pad isconnected to externals, the method comprising the steps of: (a)determining whether or not at least one connection path determined fromthe connection relationship between the internal circuits and theexternals and the positions of the at least one first conductive pad andthe second conductive pad can be connected by wire bonding; (b)calculating the position of the at least one wire bond island providedon the first semiconductor chip if it is determined in the step (a) thatthe at least one connection path can be connected by wire bonding; and(c) if it is determined in the step (a) that the connection path cannotbe connected by wire bonding, calculating the position of the at leastone wire bond island provided on the first semiconductor chip and thenchanging the configuration of the at least one wire bond island so thatthe connection path can be connected by wire bonding.

[0046] In accordance with the method for designing semiconductor deviceof the present invention, in connecting paths passing through wire bondislands, it is possible to prevent connecting members from contactingother components.

[0047] A plurality of the at least one first conductive pads areprovided, the plurality of at least one connection paths are determinedin the step (a), a plurality of the positions of the at least one wirebond islands are obtained in the step (b) or (c), the method preferablyfurther comprises the step of: (d) with respect to two of the pluralityof connection paths, changing the positions of the wire bond islands sothat the distances between the first conductive pads and the wire bondislands are equal.

[0048] A semiconductor device that a skew generated at two connectionpaths by the difference between distances from the first conductive padto a wire bond island is reduced can be obtained.

[0049] In accordance with the present invention, a method for designingsemiconductor device which comprises a first semiconductor chip thatincludes a first internal circuit and a first conductive pad which isprovided on its upper surface and is connected to the first internalcircuit; and a second semiconductor chip provided on the firstsemiconductor chip that includes a second internal circuit and a secondconductive pad which is provided on its upper surface and is connectedto the second internal circuit, wherein the first conductive pad isconnected to the second conductive pad, and the first conductive pad isconnected to externals, the method comprising the steps of: (a)determining a connection path from the connection relationship betweenthe internal circuits and the externals and the positions of theconductive pads; (b) when the connection path is connected by aconnecting member, determining whether or not a delay value of theconnection path is within a tolerance; and (c) if it is determined inthe step (b) that the delay value of the connection path is not within atolerance, changing the connecting member so that the delay value of theconnection path is within a tolerance.

[0050] In accordance with the method for designing semiconductor deviceof the present invention, a delay value can be adjusted for each of theconnection paths.

[0051] In the step (c), materials for the connecting member are changedso that the delay value of the connection path is within a tolerance.

[0052] In the step (c), the number of wires structuring the connectingmember is changed so that the delay value of the connection path iswithin a tolerance.

[0053] In accordance with the present invention, a method for designingsemiconductor device which comprises a first semiconductor chip and asecond semiconductor chip provided on the first semiconductor chip,comprising the steps of: (a) determining the area on the firstsemiconductor chip that the second semiconductor chip is to be disposedfrom the arrangement relationship between the first semiconductor chipand the second semiconductor chip and configurations of the firstsemiconductor chip and second semiconductor chip; and (b) in order toform a first convex portion with which the second semiconductor chipengages, determining the arrangement of the first convex portion on thefirst semiconductor chip and the configuration of the first convexportion.

[0054] In accordance with the method for designing semiconductor deviceof the present invention, a semiconductor device that the secondsemiconductor chip is securely fixed on the first semiconductor chipwithout misalignment can be obtained.

[0055] Preferably, the method for designing semiconductor device furthercomprises the step of: (c) in order to form a second convex portion onwhich the second semiconductor chip can slide, determining thearrangement of the second convex portion on the first semiconductor chipand the configuration of the second convex portion.

[0056] Even if the second semiconductor chip is disposed at positionsother than the area that the second semiconductor chip should beoriginally disposed when being fixed on the first semiconductor chip,the second semiconductor chip slides on the second convex portions andthen is fixed on the area defined by the first convex portions.

[0057] In accordance with the present invention, a method for designingsemiconductor device which comprises a first semiconductor chip and atleast one second semiconductor chip provided on the first semiconductorchip, comprising the steps of: (a) determining the area on the firstsemiconductor chip that the at least one second semiconductor chip is tobe disposed from the arrangement relationship between the firstsemiconductor chip and the at least one second semiconductor chip andconfigurations of the first semiconductor chip and the at least onesecond semiconductor chip; (b) detecting the number of the at least onesecond semiconductor chips; (c) if the number of the at least one secondsemiconductor chips is 1 in the step (b), determining the positions of afirst engagement portion on the first semiconductor chip and a secondengagement portion on the second semiconductor chip which is fitted intothe first engagement portion and the configurations of the firstengagement portion and the second engagement portion; and (d) if thenumber of the at least one second semiconductor chips is a pluralnumber, determining the positions of the first engagement portions onthe first semiconductor chip and the second engagement portions on thesecond semiconductor chips fitted into the first engagement portions andthe configurations of the first engagement portions and the secondengagement portions.

[0058] In accordance with the method for designing semiconductor deviceof the present invention, when fixed on the first semiconductor chip,the second semiconductor chip is securely fixed on the firstsemiconductor chip without misalignment. If a second semiconductor chipis mistaken for another second semiconductor chip, the respective secondsemiconductor chips cannot be fixed on the first semiconductor chip.Thus, it is possible to prevent a mistake among a plurality of secondsemiconductor chips.

[0059] In accordance with the present invention, a method for designingsemiconductor device which comprises a first semiconductor chip and atleast one second semiconductor chip provided on the first semiconductorchip, comprising the steps of: (a) determining the area on the firstsemiconductor chip that the at least one second semiconductor chip is tobe disposed from the arrangement relationship between the firstsemiconductor chip and the at least one second semiconductor chip andthe configurations of the first semiconductor chip and the at least onesecond semiconductor chip; (b) detecting the number of the at least onesecond semiconductor chips; (c) if the number of the at least one secondsemiconductor chips is 1 in the step (b), determining the configurationof a mark indicating the position on the first semiconductor chip thatthe second semiconductor chip is to be provided; and (d) if the numberof the at least one second semiconductor chips is a plural number in thestep (b), determining the configuration of marks indicating thepositions on the first semiconductor chip that the second semiconductorchips are to be provided.

[0060] In accordance with the method for designing semiconductor deviceof the present invention, when fixed on the first semiconductor chip,the second semiconductor chip can be prevented from mistaken for othersemiconductor chips. Further, when a plurality of second semiconductorchips are fixed on the first semiconductor chip, a mistake among theplurality of second semiconductor chips can be prevented.

[0061] In accordance with the present invention, a method for designingsemiconductor device which comprises an internal circuit, comprising thestep of determining, from a netlist and the configuration ofsemiconductor chip, the positions of wire bonding pad provided on thesemiconductor chip and connected to the internal circuit and bumpconnection pad connected to the internal circuit in parallel with thewire bonding pad.

[0062] In accordance with the method for designing semiconductor deviceof the present invention, a semiconductor device that a connectionmethod can be selected if desired can be obtained.

[0063] In accordance with the present invention, a method for designingsemiconductor device which comprises a first semiconductor chip thatincludes a first internal circuit and a plurality of first conductivepad provided on its upper surface; and a second semiconductor chipprovided on the first semiconductor chip that includes a second internalcircuit and a plurality of conductive pads provided on it upper surface,wherein the first conductive pads are connected to the second conductivepads, and a ground potential is supplied to at least one of theplurality of first conductive pads, the method comprising the step ofselecting a first conductive pad and a second conductive pad with aground potential being applied thereto from the connection relationshipbetween the internal circuits and the positions of the conductive pads.

[0064] In accordance with the method for designing semiconductor deviceof the present invention, a semiconductor device that by connectingselected first and second conductive pads to a ground potential by wirebonding, the space between the first semiconductor chip and the secondsemiconductor chip is substantially electrically shielded and EMI(Electro Magnetic Interference) is suppressed and prevented can beobtained.

[0065] In accordance with the present invention, a computer readablerecording medium incorporated into a computer used for designing asemiconductor device which comprises a first semiconductor chip thatincludes a first internal circuit, a first conductive pad which isprovided on its upper surface and is connected to the first internalcircuit and a wire bond island serving as a conductive pad which isprovided on its upper surface and is not connected to the first internalcircuit and a second semiconductor chip provided on the firstsemiconductor chip which includes a second internal circuit and a secondconductive pad which is provided on its upper surface and is connectedto the second internal circuit, wherein the first conductive pad isconnected to the second conductive pad and the conductive pad isconnected to externals, recorded in the recording medium is the programfor a computer to perform the steps of: (a) determining a connectionpath which can be connected by wire bonding from the connectionrelationship between the internal circuits and the externals and thepositions of the conductive pads; and (b) calculating, with respect tothe connection path, the position of the wire bond island provided onthe first semiconductor chip.

[0066] In accordance with the present invention, a computer readablerecording medium incorporated into a computer used for designing asemiconductor device which comprises a first semiconductor chip thatincludes a first internal circuit, at least one first conductive padwhich is provided on it upper surface and is connected to the firstinternal circuit and at least one wire bond island serving as aconductive pad which is provided on its upper surface and is notconnected to the first internal circuit and a second semiconductor chipprovided on the first semiconductor chip that includes a second internalcircuit and a second conductive pad which is provided on its uppersurface and is connected to the second internal circuit, wherein the atleast one first conductive pad is connected to the second conductivepad, and the at least one first conductive pad is connected toexternals, recorded in the recording medium is the program for acomputer to perform the steps of: (a) determining whether or not atleast one connection path determined from the connection relationshipbetween the internal circuits and the externals and the positions of theat least one first conductive pad and the second conductive pad can beconnected by wire bonding; (b) if it is determined in the step (a) thatthe at least one connection path can be connected by wire bonding,calculating the position of the at least one wire bond island providedon the first semiconductor chip; and (c) if it is determined in the step(a) that the connection path cannot be connected by wire bonding,calculating the position of the at least one wire bond island providedon the first semiconductor chip and then changing the configuration ofthe at least one wire bond island so that the connection path can beconnected by wire bonding.

[0067] In accordance with the present invention, a computer readablerecording medium incorporated into a computer used for designing asemiconductor device which comprises a first semiconductor chip thatincludes a first internal circuit and a first conductive pad which isprovided on it upper surface and is connected to the first internalcircuit and a second semiconductor chip provided on the firstsemiconductor chip that includes a second internal circuit and a secondconductive pad which is provided on its upper surface and is connectedto the second internal circuit, wherein the first conductive pad isconnected to the second conductive pad and the first conductive pad isconnected to externals, recorded in the recording medium is the programfor a computer to perform the steps of: (a) determining a connectionpath from the connection relationship between the internal circuits andthe externals and the positions of the conductive pads; (b) when theconnection path is connected by a connecting member, determining whetheror not a delay value of the connection path is within a tolerance; and(c) if it is determined in the step (b) that the delay value of theconnection path is not within a tolerance, changing the connectingmember so that the delay of the connection path is within a tolerance.

[0068] In accordance with the present invention, a computer readablerecording medium incorporated into a computer used for designing asemiconductor device which comprises a first semiconductor chip and asecond semiconductor chip provided on the first semiconductor chip,recorded in the recording medium is the program for a computer toperform the steps of: (a) determining the area on the firstsemiconductor chip that the second semiconductor chip is to be mountedfrom the arrangement relationship between the first semiconductor chipand the second semiconductor chip and the configurations of the firstsemiconductor chip and the second semiconductor chip; and (b)determining the arrangement of a first convex portion on the firstsemiconductor chip and the configuration of the first convex portion inorder to form the first convex portion the second semiconductor chipengages with.

[0069] In accordance with the present invention, a computer readablerecording medium incorporated into a computer used for designing asemiconductor device which comprises a first semiconductor chip and atleast one second semiconductor chip provided on the first semiconductorchip, recorded in the recording medium is the program for a computer toperform the steps of: (a) determining the area on the firstsemiconductor chip that the at least one second semiconductor chip is tobe disposed from the arrangement relationship between the firstsemiconductor chip and the at least one second semiconductor chip andthe configurations of the first semiconductor chip and the at least onesecond semiconductor chip; (b) detecting the number of the at least onesecond semiconductor chips; (c) if the number of the at least one secondsemiconductor chips is 1 in the step (b), determining the positions of afirst engagement portion on the first semiconductor chip and a secondengagement portion on the second semiconductor chip fitted into thefirst engagement portion and the configurations of the first engagementportion and the second engagement portion; and (d) if the number of theat least one second semiconductor chips is a plural number in the step(b), determining the positions of the first engagement portions on thefirst semiconductor chip and the second engagement portions on thesecond semiconductor chips fitted into the first engagement portions andthe configurations of the first engagement portions and the secondengagement portions.

[0070] In accordance with the present invention, a computer readablerecording medium incorporated into a computer used for designing asemiconductor device which comprises a first semiconductor chip and atleast one second semiconductor chip provided on the first semiconductorchip, recorded in the recording medium is the program for a computer toperform the steps of: (a) determining the area on the firstsemiconductor chip that the at least one second semiconductor chip is tobe disposed from the arrangement relationship between the firstsemiconductor chip and the at least one second semiconductor chip andthe configurations of the first semiconductor chip and the at least onesecond semiconductor chip; (b) detecting the number of the at least onesecond semiconductor chips; (c) if the number of the at least one secondsemiconductor chips is 1 in the step (b), determining the configurationof a mark indicating the position on the first semiconductor chip thatthe second semiconductor chip is to be provided; and (d) if the numberof the at least one second semiconductor chips is a plural number in thestep (b), determining the configuration of marks indicating thepositions on the first semiconductor chip that the second semiconductorchips are to be provided.

[0071] In accordance with the present invention, a computer readablerecording medium incorporated into a computer used for designing asemiconductor device with an internal circuit, recorded in the recordingmedium is the program for a computer to perform the step of determining,from a netlist and the configuration of a semiconductor chip, thepositions of wire bonding pad provided on the semiconductor chip andconnected to the internal circuit and bump connection pad connected tothe internal circuit in parallel with the wire bonding pad.

[0072] In accordance with the present invention, a computer readablerecording medium incorporated into a computer used for designing asemiconductor device which comprises a first semiconductor chip thatincludes a first internal circuit and a plurality of first conductivepads provided on its upper surface and a second semiconductor chipprovided on the first semiconductor chip that includes a second internalcircuit and a plurality of second conductive pads provided on its uppersurface, wherein the first conductive pads are connected to the secondconductive pads and a ground potential is supplied to at least one ofthe plurality of first conductive pads, recorded in the recording mediumis the program for a computer to perform the step of selecting a firstconductive pad and a second conductive pad with the ground potentialbeing applied thereto from the connection relationship between theinternal circuits and the positions of the conductive pads.

BRIEF DESCRIPTION OF THE DRAWINGS

[0073]FIGS. 1A and 1B are perspective view illustrating the structure ofa semiconductor device of embodiment 1.

[0074]FIG. 2 is a cross-sectional view taken along a line I-I shown inFIG. 1.

[0075]FIG. 3 is a perspective view illustrating the structure of asemiconductor device of embodiment 2.

[0076]FIG. 4 is a perspective view illustrating the structure of asemiconductor device of embodiment 3.

[0077]FIG. 5 is a perspective view illustrating the structure of asemiconductor device of embodiment 4.

[0078]FIG. 6 is a perspective view illustrating the structure of asemiconductor device of embodiment 5.

[0079]FIG. 7 is a cross-sectional view taken along a line II-II shown inFIG. 6.

[0080]FIG. 8 is a perspective view illustrating the structure of asemiconductor device of embodiment 6.

[0081]FIG. 9 is a cross-sectional view taken along a line III-III shownin FIG. 8.

[0082]FIG. 10 is a typical view illustrating the structure of asemiconductor device of embodiment 7.

[0083]FIG. 11 is a typical view illustrating another structure of thesemiconductor device of embodiment 7.

[0084]FIG. 12 is a view illustrating a circuit structure.

[0085]FIG. 13 is a perspective view illustrating the structure of asemiconductor device of embodiment 8.

[0086]FIG. 14 is a cross-sectional view taken along a line V-V shown inFIG. 13.

[0087]FIG. 15 is a block diagram illustrating the structure of a designdevice of the present invention.

[0088]FIG. 16 is a flowchart illustrating operations of the designdevice in accordance with embodiment 9.

[0089]FIG. 17 is a flowchart illustrating operations of the designdevice in accordance with embodiment 10.

[0090]FIG. 18 is a flowchart illustrating operations of the designdevice in accordance with embodiment 11.

[0091]FIG. 19 is a flowchart illustrating operations of the designdevice in accordance with embodiment 12.

[0092]FIG. 20 is a flowchart illustrating operations of the designdevice in accordance with embodiment 13.

[0093]FIG. 21 is a flowchart illustrating operations of the designdevice in accordance with embodiment 14.

[0094]FIG. 22 is a flowchart illustrating operations of the designdevice in accordance with embodiment 15.

[0095]FIG. 23 is a flowchart illustrating operations of the designdevice in accordance with embodiment 16.

[0096]FIG. 24 is a flowchart illustrating operations of the designdevice in accordance with embodiment 17.

[0097]FIG. 25 is a flowchart illustrating operations of the designdevice in accordance with embodiment 18.

[0098]FIG. 26 is a flowchart illustrating operations of the designdevice in accordance with embodiment 19.

[0099]FIG. 27 is a view illustrating the structure of a conventionalsemiconductor device.

[0100]FIG. 28 is a cross-sectional view taken along a line X-X shown inFIG. 27.

DETAILED DESCRIPTION OF THE INVENTION

[0101] Embodiments of the present invention will be describedhereinafter with reference to the drawings. For convenience ofexplanation, component that are common throughout the embodiments aredenoted by the same reference numerals. The term “connect” used hereinmeans “electrically connect” unless otherwise mentioned.

[0102] —Semiconductor Device—

[0103] Embodiment 1

[0104] This embodiment will be described with reference to FIGS. 1A, 1Band 2. FIGS. 1A and 1B are perspective views showing structures ofsemiconductor devices relating to this embodiment. FIG. 2 is across-sectional view taken along a line I-I shown in FIG. 1A.

[0105] As shown in FIG. 1A, a semiconductor device 100 a of thisembodiment has a semiconductor chip B1 which has an internal circuit(not shown) and a plurality of pads 10 connected to the internal circuitand a semiconductor chip A1 which has an internal circuit (not shown)and a plurality of pads 20 connected to the internal circuit and whichis adhered on the semiconductor chip B1. As shown in FIG. 2, inaccordance with the semiconductor device 100 a of this embodiment, thesemiconductor chip A1 is fixed on the semiconductor chip B1 with anadhered portion being interposed therebetween.

[0106] The semiconductor chip B1 is provided with the plurality of pads10 connected to its internal circuit and a plurality of wire bondislands 31. The wire bond island 31 refers to as a conductive pad whichis not connected to the internal circuit of the semiconductor chip B1.

[0107] The semiconductor device 100 a of this embodiment furtherincludes wires 13, 15, 23 and 25 connecting the pads 10 for thesemiconductor B1 to the pads 20 for the semiconductor chip A1, wires 11,16, 21 and 26 connecting the pads 10 for the semiconductor chip B1 toelectrodes outside the semiconductor device 100 a (e.g., leads of leadframe and electrodes for printed wiring board) and wires 12 a, 12 b, 14a, 14 b, 17 a, 17 b, 22 a, 22 b, 24 a and 24 b connecting the pads 20for the semiconductor chip A1 via the wire bond islands 31 to externalelectrodes.

[0108] In the semiconductor device 100 a of this embodiment, supposethat the maximum distance from the wires 12 a and 12 b connecting a pad20 of the semiconductor A1 to an electrode outside the semiconductordevice 100 a to the upper surface of the semiconductor chip B1 isindicated by h1. Then, h1<h. This is applicable to the wires 14 a and 14b, the wires 17 a and 17 b and the wires 22 a and 22 b. Bent of wires asin the conventional semiconductor device 1000 is suppressed in thesemiconductor device 100 a of this embodiment. Accordingly, when wiresare provided and then the semiconductor device 100 a is to be worked,short of the wires can be prevented. Thus, yield rates for productsobtained by working the semiconductor device 100 a are improved.

[0109] By adjusting positions of the wire bond islands 31, lengths ofwires can be made equal. For example, the wire 12 a may be as long asthe wire 17 a, and the wire 12 b may be as long as the wire 17 b. Thus,skew caused by differences between the lengths of the wires is reduced.As a result, in accordance with the semiconductor device 100 a of thisembodiment, wirings for structuring synchronous circuits are easilydesigned.

[0110] In accordance with this embodiment, by adjusting the positions ofthe wire bond islands 31, the wires between the semiconductor chips A1and B1 (specifically, the wires 12 a, 14 a, 17 a, 22 a and 24 a) may bethe same length and wiring delay values may also be the same value.

[0111] Next, a semiconductor device 100 a′ shown in FIG. 1B will bedescribed. As shown in FIG. 1B, the semiconductor device 100 a′ hassubstantially same structure as that of the above-describedsemiconductor device 100 a. The semiconductor device 100 a′ is differentfrom the semiconductor device 100 a only in that the semiconductor chipB1 has the wire bond islands 31 that are not used for wire bondingconnection.

[0112] As in the semiconductor device 100 a′, when the semiconductorchip B1 has a plurality of wire bond islands 31 regardless of being usedfor wire bonding connection, a semiconductor chip which is differentfrom the semiconductor chip A1 may be mounted by using appropriate wirebond islands 31. Namely, the semiconductor B1 may be widely used.

[0113] Embodiment 2

[0114] This embodiment will be described with reference to FIG. 3. FIG.3 is a perspective view illustrating the structure of a semiconductordevice of this embodiment.

[0115] As shown in FIG. 3, a semiconductor device 100 b of thisembodiment has a semiconductor chip B2 which includes an internalcircuit (not shown) and a plurality of pads 10 connected to the internalcircuit and a semiconductor chip A2 which includes an internal circuit(not shown) and a plurality of pads 20 connected to the internal circuitand is adhered on the semiconductor chip B2.

[0116] The semiconductor chip B2 is provided with the plurality of pads10 connected to the internal circuit and wire bond islands 31 and 32.Also in this embodiment, the wire bond island refers to as a conductivepad which is not connected to the internal circuit of the semiconductorchip B2. Unlike the wire bond islands 31, the wire bond islands 32 areformed in an elliptical configuration.

[0117] Further, the semiconductor device 100 b of this embodimentincludes wires 13, 15, 23 and 25 connecting the pads 10 for thesemiconductor chip B2 to the pads 20 for the semiconductor chip A2,wires 11, 16, 21 and 26 connecting the pads 10 for the semiconductorchip B2 to external electrodes (e.g., leads of lead frame, electrodesfor printed wiring board and the like) and wires 12 a, 12 b, 17 a, 17 b,14 a, 14 b, 22 a, 22 b, 24 a and 24 b connecting the pads 20 for thesemiconductor chip A2 via the wire bond islands 31 to externalelectrodes.

[0118] In accordance with this embodiment, unlike circular wire bondislands 31, the wire bond islands 32 are formed in an ellipticalconfiguration. As shown in FIG. 3, the wire 24 b is connected to thewire bond island 32 at a portion which is different from that the wire24 a is connected. For this reason, for example, when other componentwhich becomes an obstacle when an external pad to be connected to thewire 24 b is linearly connected to the position the wire 24 a isconnected exists, the wire 24 b does not contact the other component.Namely, by changing the configuration of the wire bond islands, a degreeof freedom in wiring design is improved.

[0119] The configuration of the wire bond islands 32 is not limited toan elliptical configuration and preferably, is appropriately changed toconfigurations enabling wires to be provided most efficiently.

[0120] In accordance with this embodiment, by adjusting the positions ofthe wire bond islands 31 and 32, the wires may have the same length.Thus, skew caused by differences between the lengths of the wires isreduced. As a result, in accordance with the semiconductor device 100 bof this embodiment, wirings for structuring synchronous circuits areeasily designed.

[0121] As in the above-described embodiment 1, in accordance with thisembodiment, by adjusting the positions of the wire bond islands 31 and32, the wires between the semiconductor chips A1 and B1 (specifically,the wires 12 a, 14 a, 17 a, 22 a and 24 a) may have the same length andwiring delay values may also have the same value.

[0122] Embodiment 3

[0123] This embodiment will be described with reference to FIG. 4. FIG.4 is a perspective view illustrating the structure of a semiconductordevice of this embodiment.

[0124] As shown in FIG. 4, a semiconductor device 100 c of thisembodiment has a semiconductor chip B3 which includes an internalcircuit (not shown) and a plurality of pads 10 connected to the internalcircuit and a semiconductor chip A3 which includes an internal circuit(not shown) and a plurality of pads 20 connected to the internal circuitand is adhered on the semiconductor chip B3.

[0125] Further, the semiconductor device 100 c of this embodiment haswires 13, 15, 23 and 25 connecting the pads 10 for the semiconductorchip B3 to the pads 20 for the semiconductor chip A3, wires 11, 16, 21and 26 connecting the pads 10 for the semiconductor chip B3 to externalelectrodes (e.g., leads of lead frame, electrodes for printed wiringboard and the like) and wires 12, 14, 22 and 24 connecting the pads 20for the semiconductor chip A3 to external electrodes. The wire 13 isespecially made of gold and is different from other wires made ofaluminum.

[0126] In accordance with this embodiment, the wire 13 is made of goldwhose resistance is different from those of the other wires made ofaluminum. By selecting materials for wires for each of the wires, adelay value may be adjusted for each of the wires. Although aluminum andgold are used for forming wires in this embodiment, the presentinvention does not limit such materials. For example, silver, copper,platinum may be used.

[0127] Embodiment 4

[0128] This embodiment will be described with reference to FIG. 5. FIG.5 is a perspective view illustrating the structure of a semiconductordevice of this embodiment.

[0129] As shown in FIG. 5, a semiconductor device 100 d of thisembodiment has a semiconductor chip B4 which includes an internalcircuit (not shown) and a plurality of pads 10 connected to the internalcircuit and a semiconductor chip A4 which includes an internal circuit(not shown) and a plurality of pads 20 connected to the internal circuitand is adhered on the semiconductor chip B4.

[0130] Further, the semiconductor device 100 d of this embodiment haswires 13, 15, 23 and 25 connecting the pads 10 for the semiconductorchip B4 to the pads 20 for the semiconductor chip A4, wires 11, 16, 21and 26 connecting the pads 10 for the semiconductor chip B4 to externalelectrodes (e.g., leads of lead frame, electrodes for printed wiringboard and the like) and wires 12, 14, 22 and 24 connecting the pads 20for the semiconductor chip A4 to external electrodes. Especially in thisembodiment, the wire 25 is made of two wires.

[0131] Because of the wire 25 being made of two wires, a wiringresistance can be reduced. Namely, by adjusting the number of wires foreach of the wires, a delay value may be adjusted for each of the wires.

[0132] As described above, in accordance with this embodiment, asemiconductor device which is easily designed and manufactured and inwhich a plurality of semiconductor chips are integrally structured isobtained. A semiconductor device which is suitable for, in particular,high speed operation is obtained.

[0133] Embodiment 5

[0134] This embodiment will be described with reference to FIGS. 6 and7. FIG. 6 is a perspective view illustrating the structure of asemiconductor device of this embodiment. FIG. 7 is a cross-sectionalview taken along a line 11-11 shown in FIG. 6. In this embodiment, wiresare not shown in order to eliminate complicated descriptions.

[0135] As shown in FIGS. 6 and 7, a semiconductor device 200 of thisembodiment has a semiconductor chip B5 which includes an internalcircuit (not shown) and a plurality of pads 10 connected to the internalcircuit and a semiconductor chip A5 which includes an internal circuit(not shown) and a plurality of pads 20 connected to the internal circuitand is adhered on the semiconductor chip B5 with an adhered portionbeing interposed therebetween.

[0136] The semiconductor chip B5 further has convex portions 41 andconvex portions 40 for sliding.

[0137] The convex portions 41 are provided at corners of an area on theupper surface of the semiconductor chip B5 where the semiconductor chipA5 is to be adhered so as to define the area where the semiconductorchip A5 is to be adhered.

[0138] A large number of the convex portions 40 for sliding are providedon the area on the upper surface of the semiconductor chip B5 other thanthe area the semiconductor chip A5 is to be adhered. The convex portions40 for sliding are disposed so that areas with sufficient size andconfiguration for the semiconductor chip A5 to be adhered thereon arenot formed between the convex portions 40 for sliding.

[0139] In accordance with the semiconductor device 200 of the presentinvention, the convex portions 41 are provided on the upper surface ofthe semiconductor chip B5 so as to define the area the semiconductorchip A5 is to be adhered. Thus, when the semiconductor chip A5 is to beadhered on the semiconductor chip B5 in a process for manufacturing thesemiconductor device 200, the semiconductor chip A5 is reliably fixedwithout misalignment.

[0140] Further, in accordance with this embodiment, the convex portions40 for sliding disposed so that areas with sufficient size andconfiguration for the semiconductor chip A5 to be adhered thereon arenot formed are provided on the upper surface of the semiconductor chipB5. For this reason, even if the semiconductor chip A5 is placed on aposition other than the area where the semiconductor A5 should beoriginally adhered when being adhered on the semiconductor B5 in theprocess for manufacturing the semiconductor device 200, thesemiconductor chip A5 slides on the convex portions 40 for sliding andis surely adhered on the area defined by the convex portions 41.

[0141] The semiconductor chip A5 needs not to be aligned with thesemiconductor chip B5 when being adhered thereon.

[0142] Accordingly, in accordance with this embodiment, thesemiconductor chip A5 can be easily adhered on the semiconductor chipB5.

[0143] Embodiment 6

[0144] This embodiment will be described with reference to FIGS. 8 and9. FIG. 8 is a perspective view illustrating the structure of asemiconductor device of this embodiment. FIG. 9 is a cross-sectionalview taken along a line 111-111 shown in FIG. 8.

[0145] As shown in FIG. 8, a semiconductor device 300 of this embodimenthas a semiconductor chip B6 which includes an internal circuit (notshown) and a plurality of pads connected to the internal circuit andsemiconductor chips A6 and A6′ each of which includes an internalcircuit (not shown) and a plurality of pads connected to the internalcircuit and is provided on the semiconductor chip B6. Wires and pads arenot shown in this embodiment in order to eliminate complicateddescriptions.

[0146] Especially in accordance with this embodiment, the semiconductorchip B6 has circular openings 42 a and rectangular openings 42 b. Thesemiconductor chip A6 has convex portions 43 a with circularcross-sectional configuration and the semiconductor chip A6′ has convexportions 43 b with rectangular cross-sectional configuration. As shownin FIG. 9, the semiconductor chip A6′ is adhered to the semiconductorchip B6 with an adhered portion being interposed therebetween. Theconvex portions 43 b of the semiconductor chip A6′ are fitted into theopenings 42 b of the semiconductor chip B6. Similarly, the semiconductorchip A6 is also adhered to the semiconductor chip B6 with an adheredportion being interposed therebetween. The convex portions 43 a of thesemiconductor chip A6 are fitted into the openings 42 a of thesemiconductor chip B6.

[0147] In accordance with the semiconductor device 300 of thisembodiment, a mark 44 a for chip arrangement is printed on an area 45 aof the upper surface of the semiconductor chip B6 that the semiconductorchip A6 is adhered. A mark 44 b for chip arrangement is printed on anarea 45 b that the semiconductor chip A6′ is adhered.

[0148] In accordance with the semiconductor device 300 of thisembodiment, the semiconductor chip A6 is provided with the convexportions 43 a, the semiconductor chip A6′ is provided with the convexportions 43 b and the semiconductor chip B6 is provided with theopenings 42 b and the openings 42 a, so that when the semiconductorchips A6 and A6′ are adhered to the semiconductor chip B6, the convexportions 43 a are fitted into the openings 42 a and the convex portions43 b are fitted into the openings 42 b. Thus, when the semiconductorchips A6 and A6′ are to be adhered to the semiconductor chip B6 in aprocess for manufacturing the semiconductor device 300, thesemiconductor chip A6 is securely fixed on the semiconductor chip B6without misalignment.

[0149] Especially in accordance with this embodiment, the convexportions 43 a and the openings 42 a have a cylindrical configuration,and the convex portions 43 b and the openings 42 b have a square poleconfiguration. For this reason, if the semiconductor chip A6 is mistakenfor the semiconductor chip A6′, the semiconductor chips A6 and A6′cannot be adhered on the semiconductor chip B6. Thus, it is possible toprevent a semiconductor device from being structured with thesemiconductor A6 being mistaken for the semiconductor chip A6′.

[0150] Although the convex portions 43 a and the openings 42 a have acylindrical configuration and the convex portions 43 b and the openings42 b have a square pole configuration in this embodiment, the presentinvention is not limited such case. For example, the convex portions 43a and the openings 42 a may have any configurations including astar-shaped pole configuration, a triangle pole configuration and thelike.

[0151] The area 45 a on the semiconductor chip B6 the semiconductor chipA6 is adhered is provided with the mark 44 a for chip arrangementserving as a mark for fixing the semiconductor chip A6. The area 45 b onthe semiconductor chip B6 the semiconductor chip A6′ is adhered isprovided with the mark 44 b for chip arrangement serving as a mark forfixing the semiconductor chip A6′. Thus, when the semiconductor chips A6and A6′ are to be adhered on the semiconductor chip B6 in the processfor manufacturing the semiconductor device 300, the semiconductor chipA6 is seldom mistaken by the semiconductor chip A6′.

[0152] In accordance with this embodiment, the semiconductor chips A6and A6′ are electrically connected to the semiconductor chip B6 by wirebonding. Nevertheless, the present invention is not limited to suchcase. The semiconductor chips A6 and A6′ may be electrically connectedto the semiconductor chip B6 by bumps. Further, wire bonding and bumpconnection may be used together.

[0153] Embodiment 7

[0154] This embodiment will be described with reference to FIGS. 10 and11. FIGS. 10 and 11 are typical views illustrating the structure of asemiconductor device of this embodiment.

[0155] As shown in FIG. 10, a semiconductor device 400 of thisembodiment has a semiconductor chip B7 which includes an internalcircuit (not shown) and a plurality of pads 10 connected to the internalcircuit and a semiconductor chip A7 which includes an internal circuit(not shown) and a plurality of pads 20 for wire bonding connected to theinternal circuit and is adhered on the semiconductor chip B7. Inaccordance with the semiconductor device 400, the semiconductor chip A7is connected to the semiconductor chip B7 by wires 11 connecting thepads 10 for the semiconductor chip B7 to the pads 20 for thesemiconductor chip A7.

[0156] As shown in FIG. 11, a semiconductor device 400′ of thisembodiment has a semiconductor chip A7 which includes an internalcircuit (not shown) and a plurality of bump connection pads 30 connectedto the internal circuit and a semiconductor chip C7 which includes aninternal circuit (not shown) and a plurality of bump connection pads(not shown) provided on the lower surface thereof and connected to theinternal circuit and which is provided on the semiconductor chip A7. Inaccordance with the semiconductor device 400′, the pads 30 for thesemiconductor chip A7 are connected to the bump connection pads of thesemiconductor chip C7 by bump connection.

[0157] As shown in FIGS. 10 and 11, the semiconductor chip A7 is used inthe semiconductor devices 400 and 400′ of this embodiment.

[0158] The wire bonding pads 20 and the bump connection pads 30 areprovided on the upper surface of the semiconductor chip A7. Thus, asshown in FIG. 11, when the semiconductor chip C7 with, on its lowersurface, wires (not shown) enabling bump connection to the bump pads 30of the semiconductor chip A7 is prepared, the semiconductor chip C7 canbe bump-connected by fillip chip bonding.

[0159] The semiconductor chip A7 of this embodiment includes the bumpconnection pads 30 on its upper surface with the plurality of pads 20being provided thereat and an circuit shown in FIG. 12. FIG. 12 showsthe structure of the circuit for the semiconductor chip A7 of thisembodiment.

[0160] In accordance with this embodiment, as shown in FIG. 12, a wirebonding pad 20 and a bump connection pad 30 are connected to theinternal circuit in the semiconductor chip A7. Thus, the semiconductorchip A7 can be connected to the semiconductor chip B7 by wire bondingand to the semiconductor chip C7 by bump connection.

[0161] Accordingly, both of the semiconductor device 400 shown in FIG.10 and the semiconductor device 400′ shown in FIG. 11 can bemanufactured.

[0162] The wire bonding connection is cheaper than the bump connection.When a semiconductor device formed of semiconductor chips withsubstantially the same size is manufactured as shown in FIG. 11, thebump connection is easier.

[0163] In general, the wire bonding pads may be provided at 80 μm ofminimum intervals therebetween. On the other hand, the bump connectionpads may be provided at 5 μm of minimum intervals therebetween. Thus, inaccordance with this embodiment, when a semiconductor device must bemade compact or when semiconductor chips with high integration level areused, two semiconductor chips may be connected with each other by usingbump connection pads, so that a semiconductor device can be easilymanufactured.

[0164] As described above, in accordance with this embodiment, anoptimal connection method for structuring a semiconductor device can beselected depending on manufacturing costs, sizes of the semiconductorchips A7, B7 and C7, wiring rules and the like. Namely, a degree offreedom in designing a semiconductor chip and a semiconductor device maybe significantly improved.

[0165] Embodiment 8

[0166] This embodiment will be described with reference to FIGS. 13 and14. FIG. 13 is a perspective view illustrating a semiconductor device ofthis embodiment. FIG. 14 is a cross-sectional view taken along a lineV-V shown in FIG. 13.

[0167] As shown in FIG. 13, a semiconductor device 500 of thisembodiment has a semiconductor chip B8 which includes a plurality ofpads 10 and a semiconductor chip A8 which includes a plurality of pads20 and is adhered on the semiconductor chip B8.

[0168] Further, the semiconductor device 500 of this embodiment haswires 60 connecting the pads 10 for the semiconductor chip B8 to thepads 20 for the semiconductor chip A8 and wires 61 connecting the pads10 for the semiconductor chip B8 to externals (group potential Vss).

[0169] As shown in FIG. 14, in accordance with the semiconductor device500 of this embodiment, bump connection pads (not shown) connected to aninternal circuit (not shown) are provided on the lower surface of thesemiconductor chip A8. Bump connection pads (not shown) connected to aninternal circuit (not shown) are also provided on the upper and thelower surfaces of the semiconductor chip B8.

[0170] The internal circuit for the semiconductor chip A8 is connectedto the internal circuit for the semiconductor chip B8 by bumpconnection. The internal circuit for the semiconductor chip B8 isbump-connected to externals by using the bump connection pads providedon the lower surface of the semiconductor chip B8.

[0171] In accordance with this embodiment, since all of the plurality ofwires 60 and 61 are connected to a ground potential Vss, potentials ofthe plurality of wires 60 and 61 are fixed at the ground potential Vss.Thus, in the semiconductor device 500, the space between thesemiconductor chips A8 and B8 is substantially electrically shielded. Inaccordance with the semiconductor device 500, EMI (Electro MagneticInterference) is suppressed and prevented. Namely, in accordance withthis embodiment, a semiconductor device with significantly highreliability is obtained.

[0172] —Method For Designing Semiconductor Device—

[0173] A method for designing the semiconductor devices 100 a to 100 d,and 200 to 500 shown in the above-described embodiments 1 to 8 in orderto manufacture the same will be described hereinafter. FIG. 15 is ablock diagram illustrating the structure of design device used formanufacturing the semiconductor devices 100 a to 100 d and 200 to 500.

[0174] As shown in FIG. 15, a design device 600 of this embodimentcomprises an input section 71 data is inputted, a CPU 72 which treatsthe data inputted to the input section 71, a database 73 which storesthe data, an output section 74 which outputs results of treatment in theCPU 72, a wire bond island forming section 80 for forming wire bondislands, a wire bond island configuration changing section 81 forchanging configurations and materials for wire bond islands determinedby the wire bond island forming section 80, an equal length pathdetermining section 82 for determining connection paths whose lengthsshould be equal, a delay determining section 83 for determining a delay,a wire material changing section 84 changing to wire materials withdelay values within a range determined by the delay determining section83, a number-of-wires changing section 85 for changing to the number ofwires in order to obtain a delay value within a range determined by thedelay determining section 83, a convex portion forming section 86 forforming convex portions defining an area a semiconductor chip is to bedisposed, a convex-portion-for-sliding forming section 87 for formingconvex portions enabling sliding of semiconductor chips, a fittingconfiguration forming section 88 for forming configurations fitting witheach other when two semiconductor chips are adhered with each other, afitting configuration changing section 89 for changing fittingconfigurations determined by the fitting configuration forming section88, a mark-for-chip-arrangement forming section 90 for forming a markfor chip arrangement on the surface of semiconductor chip, amark-for-chip-arrangement changing section 91 for changing a mark forchip arrangement determined by the chip-for-mark-arrangement formingsection 90, a pad forming section 92 for forming wire bonding pads andbump connection pads and a wire shield forming section 93 for formingwire shields.

[0175] A method for designing semiconductor device will be described inthe following embodiments with reference to FIGS. 16 to 26. Designmethods represented by flowcharts shown in FIGS. 16 to 26 are used inorder to design a semiconductor device by the design device 600.

[0176] Embodiment 9

[0177] A method for designing the semiconductor device 100 a of theembodiment 1 will be described in this embodiment. FIG. 16 is aflowchart illustrating operations of the design device 600 when thesemiconductor device 100 a of the embodiment 1 is designed.

[0178] As shown in FIG. 16, firstly in step St1, circuit structure data,inter-circuit connection data and pad position data are inputted to theinput section 71. The circuit structure data refers to as datarepresenting structures of internal circuits provided within thesemiconductor chips A1 and B1 and an external circuit the semiconductordevice 100 a is to be connected. The inter-circuit connection datarefers to as data representing the connection relationship between theinternal circuit for the semiconductor chip A1, the internal circuit forthe semiconductor chip B1 and the external circuit. The pad positiondata refers to as data representing the positions of the pads 20 for thesemiconductor chip A1, the pads 10 for the semiconductor chip B1 andexternal pads for the external circuit (leads of lead frame).

[0179] Such data are inputted to the input section 71 and then the CPU72 selects the data and stores the same in the database 73.

[0180] Next, in step St2, the CPU 72 searches, on a basis of therespective data, connection paths formed between the pads 10, the pads20 and the external pads so as to satisfy the inter-circuit connectiondata.

[0181] In step St3, the CPU 72 determines whether or not all of theconnection paths obtained by step St2 can be connected by wire bonding.If wire bonding is possible, the CPU 72 activates the wire bond islandforming section 80 and the process proceeds to step St4. If at least oneof the connection paths obtained in step St2 cannot be connected by wirebonding, the process returns to step St2 and the CPU 72 searches otherconnection paths that satisfy the inter-circuit connection data. Then,in step St3, it is determined whether or not all of the connection pathsearched again can be connected by wire bonding. Steps St2 and St3 arerepeated until all of connection paths obtained by step St2 can beconnected by wire bonding. If all connection paths can be connected bywire bonding, the CPU 72 activates the wire bond island forming section80 and the process proceed to step St4.

[0182] In step St4, the wire bond island forming section 80 calculatesthe positions on the semiconductor chip B1 that the wire bond islands 31are formed (wire bond island position data) with respect to connectionpath connecting the pads 10 to the external pads among the searchedconnection paths. The wire bond island forming section 80 makesreference to wire bond island configuration data (circular configurationdata herein) set as a default stored in advance from the database 73.

[0183] In step St5, the CPU 72 produces wire bonding performing data fora wire bonding device to perform wire bonding from the wire bond islandposition data obtained in step St4 and the wire bond islandconfiguration data.

[0184] In step St6, the output section 74 outputs the wire bondingperforming data.

[0185] By the above-described steps being performed, the semiconductordevice 100 a is designed.

[0186] In accordance with this embodiment, the semiconductor device 100a that bent of wires connecting semiconductor chips is prevented isobtained.

[0187] Embodiment 10

[0188] In accordance with this embodiment, a method for designing thesemiconductor device 100 b of the embodiment 2 will be described. FIG.17 is a flowchart illustrating operations of the design device 600 whenthe semiconductor device 100 b of the embodiment 2 is designed.

[0189] As shown in FIG. 17, firstly in step St11, circuit structuredata, data inter-circuit connection and pad position data are inputtedto the input section 71.

[0190] The circuit structure data refers to data representing structuresof the internal circuits provided within the semiconductor chips A2 andB2 and external circuit the semiconductor device 100 b is connected. Theinter-circuit connection data refers to as data representing theconnection relationship between the internal circuit for thesemiconductor chip A2, the internal circuit for the semiconductor chipB2 and the internal circuit. The pad position data refers to datarepresenting the positions of the pads 20 for the semiconductor chip A2,the pads 10 for the semiconductor chip B2 and external pads (leads oflead frame) for the external circuit.

[0191] When such data are inputted to the input section 71, the CPU 72selects the data and stores the same in the database 73.

[0192] Next, in step St12, the CPU 72 searches, on a basis of therespective data, connection paths formed between the pads 10, the pads20 and the external pads so as to satisfy the inter-circuit connectiondata.

[0193] The CPU 72 determines in step St13 whether or not all of theconnection paths obtained in step St12 can be connected by wire bonding.If connection by wire bonding is possible, the CPU 72 activates the wirebond island forming section 80 and the process proceeds to St14 a. If atleast one of the connection paths obtained in step St12 cannot beconnected by wire bonding, the CPU 72 activates the wire bond islandforming section 80 and the process proceeds to step St14 b.

[0194] In step St14 a, the wire bond island forming section 80calculates the positions on the semiconductor chip B2 that the wire bondislands 31 are to be formed (wire bond island position data) forconnection paths connecting the pads 10 to the external pads of thesearched connection paths. At this time, the wire bond island formingsection 80 makes reference to, from the database 73, wire bond islandconfiguration data (circular configuration data herein) set as a defaultstored in advance. Then, the process proceeds to step St15.

[0195] In step St14 b, the wire bond island forming section 80calculates the positions on the semiconductor chip B2 that the wire bondislands 32 are to be formed (wire bond island position data) forconnection paths connecting the pads 10 to the external pads of thesearched connection paths. At this time, the wire bond island formingsection 80 makes reference to, from the database 73, wire bond islandconfiguration data (circular configuration data herein) set as a defaultstored in advance. Then, the process proceeds to step St14 c.

[0196] In step St14 c, the wire bond island configuration changingsection 81 changes the configuration of the wire bond islands 32 bysubstituting the wire bond island configuration data (herein bysubstituting the circular configuration data set as a default byelliptical configuration data). If a delay value is extremely varied bysubstitution of the wire bond island configuration data, the wire bondisland configuration changing section 81 may optimize materials for thewire bond islands and configurations thereof in order to suppress suchvariation in the delay value. Then, the process proceeds to step St15.

[0197] In step St15, the CPU 72 produces wire bonding performing datafor a wire bonding device to perform wire bonding from the wire bondisland position data obtained in step St14 a and the wire bond islandconfiguration data obtained in step St14 c.

[0198] In step St16, the output section 74 outputs the wire bondingperforming data.

[0199] By the above-described steps being performed, the semiconductordevice 100 b is designed.

[0200] In accordance with this embodiment, the semiconductor device 100b that bent of the wires connecting the semiconductor chips is preventedcan be obtained. Especially in accordance with this embodiment, bychanging the configuration of the wire bond islands, a degree of freedomin wire bonding connection between the semiconductor chips is improved.

[0201] Embodiment 11

[0202] In accordance with this embodiment, a method for designing thesemiconductor device 100 b of the embodiment 2 will be described.

[0203]FIG. 18 is a flowchart illustrating operations of a device fordesigning semiconductor when the semiconductor device 100 b of theembodiment 2 is designed.

[0204] As shown in FIG. 18, firstly in step St21, circuit structuredata, inter-circuit connection data and pad position data are inputtedto the input section 71.

[0205] The circuit structure data refers to data representing structuresof the internal circuits provided within the semiconductor chips A2 andB2 and external circuit the semiconductor device 100 b is connected. Theinter-circuit connection data refers to as data representing theconnection relationship between the internal circuit for thesemiconductor chip A2, the internal circuit for the semiconductor chipB2 and the internal circuit. The pad position data refers to datarepresenting the positions of the pads 20 for the semiconductor chip A2,the pads 10 for the semiconductor chip B2 and external pads (leads oflead frame) for the external circuit.

[0206] When such data are inputted to the input section 71, the CPU 72selects the data and stores the same in the database 73.

[0207] Next, in step St22, the CPU 72 searches, on a basis of therespective data, connection paths formed between the pads 10, the pads20 and the external pads so as to satisfy the inter-circuit connectiondata.

[0208] The CPU 72 determines in step St23 whether or not all of theconnection paths obtained in step St22 can be connected by wire bonding.If connection by wire bonding is possible, the CPU 72 activates the wirebond island forming section 80 and the process proceeds to St24 a. If atleast one of the connection paths obtained in step St22 cannot beconnected by wire bonding, the CPU 72 activates the wire bond islandforming section 80 and the process proceeds to step St24 b.

[0209] In step St24 a, the wire bond island forming section 80calculates the positions on the semiconductor chip B2 that the wire bondislands 31 are to be formed (wire bond island position data) forconnection paths connecting the pads 10 to the external pads determinedin step St23 to be connected by wire bonding. At this time, the wirebond island forming section 80 makes reference to, from the database 73,wire bond island configuration data (circular configuration data herein)set as a default stored in advance. Then, the process proceeds to stepSt25.

[0210] In step St24 b, the wire bond island forming section 80calculates the positions on the semiconductor chip B2 that the wire bondislands 32 are to be formed (wire bond island position data) forconnection paths connecting the pads 10 to the external pads determinedin step St23 to be connected by wire bonding. At this time, the wirebond island forming section 80 makes reference to, from the database 73,wire bond island configuration data (circular configuration data herein)set as a default stored in advance. Then, the process proceeds to stepSt24 c.

[0211] In step St24 c, the wire bond island configuration changingsection 81 changes the configuration of the wire bond islands 32 bysubstituting the wire bond island configuration data (herein bysubstituting the circular configuration data set as a default byelliptical configuration data) so that the connection paths connectingthe pads 10 to the external pads determined in step St23 not to beconnected by wire bonding can be connected and the process proceeds tostep St25. If a delay value is extremely varied by substitution of thewire bond island configuration data in this step St24, the wire bondisland configuration changing section 81 may optimize materials for thewire bond islands and configurations thereof in order to suppress suchvariation in the delay value.

[0212] Next, in step St25, the CPU 72 activates the equal length pathdetermining section 82. The equal length path determining section 82determines connection paths that should be have the same length.Specifically, the equal length path determining section 82 selectsconnection paths that must be have the equal length by making referenceto the circuit structure data and the inter-circuit connection datastored in the database 73 in step St21. Then, the equal length pathdetermining section 82 makes reference to the wire bond island positiondata and the wire bond island configuration data obtained in steps St24a, St24 b and St24 c and then adjusts the wire bond island position dataso that selected connection path have the same length.

[0213] In step St26, the CPU 72 produces wire bonding performing datafor a wire bonding device to perform wire bonding from the wire bondisland position data obtained in step St25 and the wire bond islandconfiguration data obtained in steps St24 a and St24 c.

[0214] In step St27, the output section 74 outputs the wire bondingperforming data.

[0215] By the above-described steps being performed, the semiconductordevice 100 b is designed.

[0216] In accordance with this embodiment, by adjusting the positions ofthe wire bond islands 31 and 32, the semiconductor device 100 b thatspecified wires have the same length can be obtained. A skew generatedby the difference in length of wires is reduced in the wires with thesame length. Thus, the method of this embodiment is especiallypreferable when synchronous circuits must be structured in thesemiconductor device 100 b.

[0217] In accordance with this embodiment, by adjusting the positions ofthe wire bond islands 31 and 32, the wires between the semiconductorchip A1 and the semiconductor chip B1 (specifically, the wires 12 a, 14a, 17 a, 22 a and 24 a) may have the same length and wire delay valuesmay be also the same value.

[0218] Embodiment 12

[0219] A method for designing the semiconductor device 100 c of theembodiment 3 will be described in this embodiment.

[0220]FIG. 19 is a flowchart illustrating operations of the designdevice 600 when the semiconductor device 100 c of the embodiment 3 isdesigned.

[0221] As shown in FIG. 19, firstly in step St31, circuit structuredata, inter-circuit connection data, pad position data and connectiondelay tolerant data are inputted to the input section 71.

[0222] The circuit structure data refers to data representing structuresof the internal circuits provided within the semiconductor chips A3 andB3 and external circuit the semiconductor device 100 c is connected. Theinter-circuit connection data refers to as data representing theconnection relationship between the internal circuit for thesemiconductor chip A3, the internal circuit for the semiconductor chipB3 and the internal circuit. The pad position data refers to datarepresenting the positions of the pads 20 for the semiconductor chip A3,the pads 10 for the semiconductor chip B3 and external pads (leads oflead frame) for the external circuit. The connection delay tolerant datarefers to data representing the tolerance of a delay value set for everyconnection between the internal circuit for the semiconductor chip A3,the internal circuit for the semiconductor chip B3 and the externalcircuit. The tolerance of the delay value may be set, depending onspecifications of semiconductor devices, only for a specified connectionor may be set for all connections.

[0223] When such data are inputted to the input section 71, the CPU 72selects the data and stores the same in the database 73.

[0224] Next, in step St32, the CPU 72 searches, on a basis of therespective data, connection paths formed between the pads 10, the pads20 and the external pads so as to satisfy the inter-circuit connectiondata.

[0225] In step St33, the CPU 72 activates the delay determining section83. The delay determining section 83 calculates, on a basis of dataabout resistance values for wire materials stored in the database 73serving as a default, a delay value for connection paths obtained instep St32 and then determines whether or not the calculated delay valueis within a tolerance on a basis of the connection delay tolerant data.If the calculated delay value is within a tolerance, the CPU 72 proceedsto step St35. If the delay value calculated in the connection pathsobtained in step St32 is out of tolerance, the CPU 72 activates the wirematerial changing section 84 and the process proceeds to step St34.

[0226] In step St34, the wire material changing section 84 changesmaterials for wires for connection paths that the delay value obtainedin step St33 is out of tolerance. Specifically, the wire materialchanging section 84 selects materials for wires that a delay value iswithin a tolerance while making reference to data about resistance forvarious materials stored in advance in the database 73. Then, theprocess proceeds to step St35.

[0227] In step St35, the CPU 72 produces, on a basis of the connectionpaths obtained in step St33, wire bonding performing data for a wirebonding device to perform wire bonding. If the connection paths thatwire materials were changed in step St34 are provided, wire bondingperforming data is produced on a basis of obtained materials for wires.

[0228] Next, in step St36, the output section 74 outputs the wirebonding performing data.

[0229] By the above-described steps being performed, the semiconductordevice 100 c is designed.

[0230] In accordance with this embodiment, wire materials may bechanged. For this reason, a delay value may be adjusted for each of theconnection paths between the semiconductor chips.

[0231] Especially by changing to wire materials with low resistance, inaccordance with this embodiment, a semiconductor device in which awiring resistance between semiconductor chips is reduced and which iscapable of operating at high speed can be obtained.

[0232] Embodiment 13

[0233] A method for designing the semiconductor device 100 d of theembodiment 4 will be described in this embodiment.

[0234]FIG. 20 is a flowchart illustrating operations of a device fordesigning semiconductor when the semiconductor device 100 d of theembodiment 4 is designed.

[0235] As shown in FIG. 20, firstly in step St41, circuit structuredata, inter-circuit connection data, pad position data and connectiondelay tolerant data are inputted to the input section 71.

[0236] The circuit structure data refers to data representing structuresof the internal circuits provided within the semiconductor chips A4 andB4 and external circuit the semiconductor device 100 d is connected. Theinter-circuit connection data refers to as data representing theconnection relationship between the internal circuit for thesemiconductor chip A4, the internal circuit for the semiconductor chipB4 and the internal circuit. The pad position data refers to datarepresenting the positions of the pads 20 for the semiconductor chip A4,the pads 10 for the semiconductor chip B4 and external pads (leads oflead frame) for the external circuit. The connection delay tolerant datarefers to data representing the tolerance of a delay value set for everyconnection between the internal circuit for the semiconductor chip A4,the internal circuit for the semiconductor chip B4 and the externalcircuit. The tolerance of the delay value may be set, depending onspecifications of semiconductor devices, only for a specified connectionor may be set for all connections.

[0237] When such data are inputted to the input section 71, the CPU 72selects the data and stores the same in the database 73.

[0238] Next, in step St42, the CPU 72 searches, on a basis of therespective data, connection paths formed between the pads 10, the pads20 and the external pads so as to satisfy the inter-circuit connectiondata.

[0239] In step St43, the CPU 72 calculates, on a basis of data aboutresistance values for wire materials stored in the database 73 servingas a default, a delay value for connection paths obtained in step St42and then determines whether or not the calculated delay value is withina tolerance on a basis of the connection delay tolerant data. If thecalculated delay value is within a tolerance, the CPU 72 proceeds tostep St45. If the delay value calculated in the connection pathsobtained in step St42 is out of tolerance, the CPU 72 activates thenumber-of-wires changing section 85 and the process proceeds to stepSt44.

[0240] In step St44, the number-of-wires changing section 85 changes thenumber of wires for the connection paths that the delay value obtainedin step St43 is out of tolerance. Specifically, the number-of-wireschanging section 85 makes reference to data about resistance values forwire materials stored as a default in advance in the database 73 andthen selects the number of wires that a delay value is within thetolerance. Then, the process proceeds to step St45.

[0241] In step St45, the CPU 72 produces, on a basis of the connectionpaths obtained in step St43, wire bonding performing data for a wirebonding device to perform wire bonding. If there may be includedconnection paths with the number of wires having been changed in stepSt44, wire bonding performing data is produced on a basis of theobtained number of wires.

[0242] Next, in step St46, the output section 74 outputs the wirebonding performing data.

[0243] By the above-described steps being performed, the semiconductordevice 100 d is designed.

[0244] In accordance with this embodiment, a delay value may be adjustedfor each of the connection paths between the semiconductor chips bychanging the number of wires.

[0245] Especially by increasing the number of wires, in accordance withthis embodiment, a semiconductor device which has reduced wiringresistance between semiconductor chips and is capable of operating athigh speed can be obtained.

[0246] Embodiment 14

[0247] This embodiment will describe a method for designing thesemiconductor device 200 of the embodiment 5. In accordance with thisembodiment, the convex portions 40 for sliding are not formed. FIG. 21shows a flowchart illustrating operations of the design device 600 whenthe semiconductor device 200 of the embodiment 5 without the convexportions 40 for sliding being provided thereat is designed.

[0248] As shown in FIG. 21, firstly in step St51, semiconductor chiparrangement data and semiconductor chip configuration data are inputtedto the input section 71.

[0249] The semiconductor chip arrangement data refers to datarepresenting an arrangement relationship when the semiconductor chip A5is adhered on the semiconductor chip B5. The semiconductor chipconfiguration data refers to data representing configurations of thesemiconductor chips A5 and B5.

[0250] When the respective data are inputted to the input section 71,the CPU 72 selects the data and stores the same in the database 73.

[0251] Next, in step St52, the CPU 72 determines, from the respectivedata, the area on the semiconductor chip B5 that the semiconductor chipA5 is to be disposed.

[0252] In step St53, the CPU 72 activates the convex portion formingsection 86. The convex portion forming section 86 calculates convexportion forming data (coordinates and configurations) for forming theconvex portions 41 confining the area that the semiconductor chip A5 isto be disposed obtained in step St52 on the upper surface of thesemiconductor chip B2. Specifically, the convex portion forming section86 makes reference to various convex portion forming data already storedin the database 73 and selects optimum convex portion forming data.

[0253] In step St54, the CPU 72 produces, on a basis of the convexportion forming data obtained in step St53, semiconductor chipconfiguration data representing the configuration of the semiconductorchip B5.

[0254] In step St55, the output section 74 outputs the semiconductorchip configuration data.

[0255] By the above-described steps being performed, the semiconductordevice 200 is designed.

[0256] In accordance with this embodiment, the convex portions 41 forconfining the area that the semiconductor chip A5 is to be adhered aredesigned on the upper surface of the semiconductor chip B5. Thus, whenthe two semiconductor chips are adhered with each other in a process formanufacturing a semiconductor device, the semiconductor chip A5 issecurely fixed on the semiconductor chip B5 without misalignment.

[0257] Namely, by confining the configuration of an area semiconductorchips are junctioned, semiconductor devices can be easily adhered witheach other.

[0258] Embodiment 15

[0259] This embodiment will describe a method for designing thesemiconductor device 200 of the embodiment 5. FIG. 22 shows a flowchartillustrating operations of the design device 600 when the semiconductordevice 200 of the embodiment 5 is designed.

[0260] As shown in FIG. 22, firstly in step St61, semiconductor chiparrangement data and semiconductor chip configuration data are inputtedto the input section 71.

[0261] The semiconductor chip arrangement data refers to datarepresenting an arrangement relationship when the semiconductor chip A5is adhered on the semiconductor chip B5. The semiconductor chipconfiguration data refers to data representing configurations of thesemiconductor chips A5 and B5.

[0262] When the respective data are inputted to the input section 71,the CPU 72 selects the data and stores the same in the database 73.

[0263] Next, in step St62, the CPU 72 determines, from the respectivedata, the areas that the semiconductor chip A5 the semiconductor chip B5are to be disposed.

[0264] In step St63, the CPU 72 activates the convex portion formingsection 86. The convex portion forming section 86 calculates convexportion forming data (coordinates and configurations) for forming theconvex portions 41 confining the area that the semiconductor chip A5 isto be disposed obtained in step St62. Specifically, the convex portionforming section 86 makes reference to various convex portion formingdata already stored in the database 73 and selects optimum convexportion forming data.

[0265] In step St64, the CPU 72 activates the convex-portion-for-slidingforming section 87. The convex-portion-for-sliding forming section 87calculates convex-portion-for-sliding forming data (coordinates andconfigurations) for forming the convex portion 40 for sliding at areasother than the area obtained in step St62 that the semiconductor chip A5is to be disposed. The convex portions 40 for sliding are formed so thatan area with sufficient size and configuration for the semiconductorchip A5 to be adhered is not formed. Specifically, theconvex-portion-for-sliding forming section 87 makes reference to variousconvex-portion-for-sliding forming data already stored in the database73 and then selects optimum convex-portion-for-sliding forming data.

[0266] In step St65, the CPU 72 produces, on a basis of the convexportion forming data and the convex-portion-for-sliding forming data,semiconductor chip configuration data representing the configuration ofthe semiconductor chip B5.

[0267] In step St66, the output section 74 outputs the semiconductorchip configuration data.

[0268] By the above-described steps being performed, the semiconductordevice 200 is designed.

[0269] In accordance with this embodiment, the convex portions 40 forsliding disposed so that an area with sufficient size and configurationfor the semiconductor chip A5 to be adhered is not formed are designedon the upper surface of the semiconductor chip B5. Thus, even if thesemiconductor chip A5 is disposed at positions other than the area thatthe semiconductor chip A5 should be originally disposed when beingadhered on the semiconductor chip B5 in a process for manufacturing thesemiconductor device 200, the semiconductor chip A5 slides on the convexportions 40 for sliding and then is reliably adhered at the areaconfined by the convex portions 41.

[0270] Namely, when the semiconductor chip A5 is adhered on thesemiconductor chip B5, their alignment needs not to be performed.Accordingly, in accordance with this embodiment, the semiconductor chipA5 can be easily adhered on the semiconductor chip B5.

[0271] Embodiment 16

[0272] This embodiment will describe a method for designing thesemiconductor device 300 of the embodiment 6. Here, in accordance withthis embodiment, the marks 44 a and 44 b for chip arrangement are notformed. FIG. 23 is a flowchart illustrating operations of the designdevice 600 when the semiconductor device 300 of the embodiment 6 withoutthe marks 44 a and 44 b for chip arrangement being provided thereat isdesigned.

[0273]FIG. 23 is a flowchart illustrating operations of the designdevice 600 when the semiconductor device 300 of the embodiment 6 isdesigned.

[0274] As shown in FIG. 23, firstly in step St71, semiconductor chiparrangement data and semiconductor chip configuration data are inputtedto the input section 71.

[0275] The semiconductor chip arrangement data refers to datarepresenting an arrangement relationship when the semiconductor chips A6and A6′ are adhered on the semiconductor chip B6. The semiconductor chipconfiguration data refers to data representing the configurations of thesemiconductor chips A6, A6′ and B6.

[0276] When the respective data are inputted to the input section 71,the CPU 72 selects the data and stores the same in the database 73.

[0277] In step St72, the CPU 72 searches, from the respective data, thepositions that the semiconductor chips A6, B6 and C6 are to be disposed.

[0278] In step St73, it is determined whether or not a plurality ofsemiconductor chips are to be mounted on a semiconductor chip(multi-chip mounting). In a case of the multi-chip mounting as in thisembodiment, the process proceeds to step St74 b. Otherwise, the stepproceeds to step St74 a.

[0279] In step St74 a, the CPU 72 activates the fitting configurationforming section 88. The fitting configuration forming section 88determines fitting configuration forming data (coordinates andconfigurations) used for forming configurations fitting with each other(e.g., the convex portion 43 a and the opening 42 a shown in FIG. 8) attwo semiconductor chips when the two semiconductor chips are to beadhered with each other. At this time, the fitting configuration formingsection 88 makes reference to fitting configuration forming data (inthis embodiment, cylindrical convex portion and cylindrical opening)already stored as a default in the database 73. Then, the processproceeds to step St75.

[0280] In step St74 b, the CPU 72 activates the fitting configurationforming section 88. The fitting configuration forming section 88calculates fitting configuration data (coordinates and configurations)used for forming configurations fitting with each other (the convexportion 43 a and the opening 42 a, and the convex portion 43 b and theopening 42 b) on the semiconductor chips when the semiconductor chipsare adhered with each other. At this time, the fitting configurationforming section 88 makes reference to fitting configuration forming dataalready stored as a default in the database 73 (in this embodiment, thecylindrical convex portion 43 a and 43 b, and the cylindrical convexportion and the opening portion 42 a and 42 b). Then, the processproceeds to step St74 c.

[0281] In step St74 c, the CPU 72 activates the fitting configurationchanging section 89. The fitting configuration changing section 89changes the fitting configuration forming data obtained in step St74 bso that mounted semiconductor chips have different configurations. Inaccordance with this embodiment, the configuration of fitted portions ofthe semiconductor chips A6 and B6 (cylindrical configuration) isdifferent from that of fitted portions of the semiconductor chips A6′and B6 (square pole configuration).

[0282] In step St75, the CPU 72 produces, on a basis of the fittingconfiguration forming data, semiconductor chip configuration datarepresenting the configurations of semiconductor chips (in thisembodiment, the semiconductor chips A6, A6′ and B6).

[0283] In step St76, the output section 74 outputs the semiconductorchip configuration data.

[0284] By the above-described steps being performed, the semiconductordevice 300 is designed.

[0285] In accordance with this embodiment, the convex portions 43 a aredesigned on the semiconductor chip A6, the convex portions 43 b aredesigned on the semiconductor chip A6′ and the openings 42 a and 42 bare designed on the semiconductor chip B6 such that when thesemiconductor chips A6 and A6′ are adhered on the semiconductor chip B6,the convex portions 43 a are fitted into the openings 42 a and theconvex portions 43 b are fitted into the opening portions 42 b. Thus,the semiconductor chip A6 is securely fixed without misalignment whenbeing adhered on the semiconductor chip B6 together with thesemiconductor chip A6′ in a process for manufacturing the semiconductordevice 300.

[0286] Further, in accordance with this embodiment, the convex portions43 a and the opening portions 42 a are designed in a cylindricalconfiguration. The convex portions 43 b and the opening portions 42 bare designed in a square pole configuration. Thus, if the semiconductorchip A6 is mistaken for the semiconductor chip A6′, the semiconductorchips A6 and A6′ cannot be adhered on the semiconductor chip B6.Accordingly, it is possible to prevent a semiconductor device from beingstructured with the semiconductor chip A6 being mistaken for thesemiconductor chip A6′. Namely, when the semiconductor device has amulti-chip structure, a semiconductor device that mistakes of adheringsemiconductor chips can be prevented can be designed.

[0287] Although the convex portions 43 a and the opening portions 42 aare formed in a cylindrical configuration and the convex portion 43 band the opening portions 42 b are formed in a square pole configurationin this embodiment, the present invention is not limited to such case.For example, the convex portions 43 a and the opening portions 42 a mayhave any configurations including a star-shaped configuration and atriangular pole configuration.

[0288] Embodiment 17

[0289] This embodiment will describe a method for designing thesemiconductor device 300 of the embodiment 6. Here, in accordance withthis embodiment, the convex portions 43 a and 43 b, and the openingportions 42 a and 42 b are not formed. FIG. 24 is a flowchartillustrating operations of the design device 600 when the semiconductordevice 300 of the embodiment 6 without the convex portions 43 a and 43 band the opening portions 42 a and 42 b being provided thereat isdesigned.

[0290]FIG. 24 is a flowchart illustrating operations of the designdevice 600 when the semiconductor device 300 of the embodiment 6 isdesigned.

[0291] As shown in FIG. 24, firstly in step St81, semiconductor chiparrangement data and semiconductor chip configuration data are inputtedto the input section 71.

[0292] The semiconductor chip arrangement data refers to datarepresenting an arrangement relationship when the semiconductor chips A6and A6′ are adhered on the semiconductor chip B6. The semiconductor chipconfiguration data refers to data representing the configurations of thesemiconductor chips A6, A6′ and B6.

[0293] When the respective data are inputted to the input section 71,the CPU 72 selects the data and stores the same in the database 73.

[0294] In step St82, the CPU 72 searches, from the respective data, thepositions that the semiconductor chips A6, B6 and C6 are to be disposed.

[0295] In step St83, it is determined whether or not a plurality ofsemiconductor chips are to be mounted on a semiconductor chip(multi-chip mounting). In a case of the multi-chip mounting as in thisembodiment, the process proceeds to step St84 b. Otherwise, the stepproceeds to step St84 a.

[0296] In step St84 a, the CPU 72 activates the chip arrangement markforming section 90. The chip arrangement mark forming section 90determines chip arrangement mark forming data (coordinates andconfigurations) used for forming chip arrangement marks (e.g., the chiparrangement mark 44 a shown in FIG. 8 and the like) serving as a markused when two semiconductor chips are to be adhered with each other. Atthis time, the chip arrangement mark forming section 90 makes referenceto chip arrangement mark forming data (in this embodiment, characterssuch as L and R) already stored as a default in the database 73. Then,the process proceeds to step St85.

[0297] In step St84 b, the CPU 72 activates the chip arrangement markforming section 90. The chip arrangement mark forming section 90determines chip arrangement mark forming data (coordinates andconfigurations) used for forming the chip arrangement marks 44 a and 44b serving as a mark utilized when semiconductor chips are adhered witheach other on the semiconductor chips when the semiconductor chips areadhered with each other. At this time, the chip arrangement mark formingsection 90 makes reference to the chip arrangement mark forming dataalready stored as a default in the database 73 (in this embodiment,characters such as L and R). Then, the process proceeds to step St85.

[0298] In step St84 c, the CPU 72 activates the chip arrangement markchanging section 91. The chip arrangement mark changing section 91changes the chip arrangement mark forming data obtained in step St84 bso that chip arrangement marks are different for each mountedsemiconductor chip. In accordance with this embodiment, the mark on thesemiconductor chips A6 and B6 (“L” of the chip arrangement mark 44 a) isdifferent from that on the semiconductor chips A6′ and B6 (“R” of thechip arrangement mark 44 b).

[0299] In step St85, the CPU 72 produces, on a basis of the chiparrangement mark forming data, semiconductor chip configuration datarepresenting the configurations of semiconductor chips (in thisembodiment, the semiconductor chips A6, A6′ and B6).

[0300] In step St86, the output section 74 outputs the semiconductorchip configuration data.

[0301] By the above-described steps being performed, the semiconductordevice 300 is designed.

[0302] In accordance with this embodiment, the chip arrangement mark 44a for disposing the semiconductor chip A6 is designed at the area on thesemiconductor chip B6 that the semiconductor chip A6 is to be adhered.Similarly, the chip arrangement mark 44 b for disposing thesemiconductor chip A6′ is designed at the area on the semiconductor chipB6 that the semiconductor chip A6′ is to be adhered. Thus, thesemiconductor chip A6 is seldom mistaken for the semiconductor chip A6′when being adhered on the semiconductor chip B6 together with thesemiconductor chip A6′ in a process for manufacturing the semiconductordevice 300.

[0303] Embodiment 18

[0304] This embodiment will describe a method for designing thesemiconductor chip A7 for structuring the semiconductor devices 400 and400′ of the embodiment 7. FIG. 25 is a flowchart illustrating operationsof the design device 600 when the semiconductor chip A7 of theembodiment 7 is designed.

[0305]FIG. 25 is a flowchart illustrating operations of the designdevice 600 when the semiconductor chip A7 of the embodiment 7 isdesigned.

[0306] As shown in FIG. 25, firstly in step St91, a netlist for theinternal circuit of the semiconductor chip A7 and data of theconfiguration of the semiconductor chip A7 are inputted to the inputsection 71. When the respective data are inputted to the input section71, the CPU 72 selects the data and stores the same in the database 73.

[0307] In step St92, the CPU 72 determines, from the respective data,the positions on the semiconductor chip A7 that the wire bonding pads 20and the bump connection pads 30 connected in parallel to the internalcircuit are disposed.

[0308] In step St93, the CPU 72 activates the pad forming section 92.The pad forming section 92 calculates pad forming data on a basis of thepositions of the pads obtained in step St92 and the pad configurationdata stored in advance in the database 73.

[0309] In step St94, the CPU 72 produces, on a basis of the pad formingdata, semiconductor chip configuration data representing theconfiguration of the semiconductor chip A7.

[0310] In step St95, the output section 74 outputs the semiconductorchip configuration data.

[0311] By the above-described steps being performed, the semiconductorchip A7 is designed.

[0312] In accordance with this embodiment, the semiconductor chip A7that comprises the wire bonding pads 20 and the bump connection pads 30connected in parallel to the internal circuit is designed. Accordingly,wiring for the semiconductor chip A7 is possible by either wire bondingor bump connection.

[0313] Thus, an optimum connection method for structuring asemiconductor device can be selected depending on sizes of semiconductorchip to be adhered to the semiconductor chip A7 and wiring rules.Namely, a degree of freedom in designing a semiconductor chip and asemiconductor device is extremely improved.

[0314] Embodiment 19

[0315] This embodiment will describe a method for designing thesemiconductor device 500 of the embodiment 8. FIG. 26 is a flowchartillustrating operation of the design device 600 when the semiconductordevice 500 of the embodiment 8 is designed.

[0316] As shown in FIG. 26, firstly in step St101, circuit structuredata, inter-circuit connection data and pad position data are inputtedto the input section 71.

[0317] Circuit structure data refers to data representing the structuresof the internal circuits provided respectively within the semiconductorchips A8 and B8 and the external circuit that the semiconductor device500 is connected. Inter-circuit connection data refers to datarepresenting the connection relationship between the internal circuitfor the semiconductor chip A8, the internal circuit for thesemiconductor B8 and the external circuit. Pad position data refers todata representing the positions of the pads 20 for the semiconductorchip A8, the pads 10 for the semiconductor chip B8 and external pads forthe external circuit (leads of lead frame).

[0318] When the respective data are inputted to the input section 71,the CPU 72 selects the data and stores the same in the database 73.

[0319] Next, in step St102, the CPU 72 searches, by using the respectivedata, pads serving as a ground potential when two semiconductor chipsare adhered with each other among the pads for the semiconductor chipsA8 and B8.

[0320] In step St103, the CPU 72 activates the wire shield formingsection 93. The wire shield forming section 93 calculates wire shieldforming data for forming a wire shield by connecting the pads serving asa ground potential obtained in step St102.

[0321] In step St104, the CPU 72 produces wire bonding performing datafor a wire bonding device to perform wire bonding from the wire shieldforming data obtained in step St103.

[0322] In step St105, the output section 74 outputs the wire bondingperforming data.

[0323] By the above-described steps being performed, the semiconductordevice 500 is designed.

[0324] The semiconductor device 500 designed in accordance with thisembodiment is provided a shield with a ground potential. For thisreason, EMI (Electro Magnetic Interference) can be prevented in thesemiconductor device 500. OTHER EMBODIMENTS

[0325] Programs for design methods represented by the flowchartsillustrated in FIGS. 16 to 26 may be recorded in a computer readablerecording medium and then be used for designing semiconductor deviceswith a computer.

[0326] Further, the programs for design methods represented by theflowcharts illustrated in FIGS. 16 to 26 may be obtained throughelectronic information communication means and then be used fordesigning semiconductor devices with a computer. Specifically, theprograms are updated in an FTP site. Then, the programs may bedownloaded into a computer via an internet and then be used fordesigning semiconductor devices.

[0327] For example, the steps described in the embodiment 9 (the stepsshown in FIG. 16) serving as procedures are stored in a computerreadable recording medium as a program. Then, the semiconductor device100 a can be automatically designed.

[0328] Examples of the recording medium include, in addition to amagnetic tape utilizing a magnetic body, a floppy (R) disk, an HDD, anon-volatile memory such as an EEPROM and an optical disk such as a CDor a DVD, and any of them may be used.

[0329] In accordance with the present invention, a semiconductor devicewhich is easily designed and manufactured and in which a plurality ofsemiconductor chips are integrally structured can be provided.

What is claimed is:
 1. A semiconductor device comprising: a firstsemiconductor chip that includes a first internal circuit and at leastone first conductive pad which is provided on its upper surface and isnot connected to said first internal circuit; a second semiconductorchip provided on said first semiconductor chip that includes a secondinternal circuit and at least one second conductive pad which isprovided on its upper surface and connected to said second internalcircuit; at least one first connecting member for connecting said atleast one first conductive pad to said at least one second conductivepad; and at least one second connecting member led from said at leastone first conductive pad.
 2. The semiconductor device of claim 1,wherein said at least one first connecting member contacts the point onsaid at least one first conductive pad which is different from the pointsaid at least one second connecting member contacts.
 3. Thesemiconductor device of claim 1, wherein a plurality of said at leastone first conductive pads are provided, a plurality of said at least onesecond conductive pads are provided, a plurality of said at least onefirst connecting member are provided, a plurality of said at least onesecond connecting member are provided, and two of said plurality offirst connecting members have the same length.
 4. A semiconductor devicecomprising: a first semiconductor chip that includes a plurality offirst conductive pads provided on its upper surface; a secondsemiconductor chip that is provided on said first semiconductor chip andincludes a plurality of second conductive pads provided on its uppersurface; and a plurality of first connecting members for connecting saidplurality of first conductive pads to said plurality of secondconductive pads, wherein at least one of said plurality of firstconnecting members has a resistance value per unit length different fromthose of the other first connecting members.
 5. The semiconductor deviceof claim 4, wherein at least one of said plurality of first connectingmembers is made of a material different from those of the other firstconnecting members.
 6. The semiconductor device of claim 4, wherein thenumber of wires for at least one of said plurality of first connectingmembers is different from those of the other first connecting members.7. A semiconductor device comprising: a first semiconductor chip; and asecond semiconductor chip provided on said first semiconductor chip,wherein fixing means for disposing said second semiconductor chip isprovided on said first semiconductor chip.
 8. The semiconductor deviceof claim 7, wherein said fixing means is a first convex portion withwhich said second semiconductor chip can engage.
 9. The semiconductordevice of claim 8, wherein a second convex portion on which said secondsemiconductor chip can slide is formed at areas on said firstsemiconductor chip other than the area that said second semiconductorchip is to be disposed.
 10. A semiconductor device comprising: a firstsemiconductor chip; and a second semiconductor chip provided on saidfirst semiconductor chip, wherein said first semiconductor chip has afirst engagement portion, said second semiconductor chip has a secondengagement portion, and said first engagement portion is fitted intosaid second engagement portion.
 11. The semiconductor device of claim 10further comprising a third semiconductor chip provided on said firstsemiconductor chip, wherein said third semiconductor chip has a thirdengagement portion, said first semiconductor chip has a fourthengagement portion, said third engagement is fitted into said fourthengagement portion and said first engagement portion has differentconfiguration from said third engagement portion.
 12. A semiconductordevice comprising: a first semiconductor chip; and a secondsemiconductor chip provided on said first semiconductor chip, wherein afirst mark indicating the area said second semiconductor chip is to bedisposed is provided on said first semiconductor chip.
 13. Thesemiconductor device of claim 12 further comprising a thirdsemiconductor chip provided on said first semiconductor chip, wherein asecond mark indicating the area said third semiconductor chip is to bedisposed is provided on said first semiconductor chip, said first markis different from said second mark.
 14. A semiconductor devicecomprising: an internal circuit; a wire bonding conductive pad connectedto said internal circuit; and a bump connection pad connected to saidinternal circuit in parallel with said wire bond conductive pad.
 15. Thesemiconductor device of claim 14 comprising: a first surface; and asecond surface opposing said first surface, wherein said wire bondingconductive pad and said bump connection pad are provided on said firstsurface.
 16. A semiconductor device comprising: a first semiconductorchip that includes a plurality of first conductive pads provided on itupper surface; a second semiconductor chip provided on said firstsemiconductor chip that includes a plurality of second conductive padsprovided on its upper surface; a plurality of first connecting membersfor connecting said plurality of first conductive pads to said pluralityof second conductive pads; and a plurality of second connecting membersled from said plurality of second conductive pads, with a groundpotential beings supplied thereto.
 17. A method for designingsemiconductor device which comprises a first semiconductor chip thatincludes a first internal circuit, a first conductive pad which isprovided on its upper surface and is connected to said first internalcircuit and a wire bond island serving as a conductive pad which isprovided on its upper surface and is not connected to said firstinternal circuit; and a second semiconductor chip provided on said firstsemiconductor chip that includes a second internal circuit and a secondconductive pad which is provided on its upper surface and is connectedto said second internal circuit, wherein said first conductive pad isconnected to said second conductive pad, and said first conductive padis connected to externals, said method comprising the steps of: (a)determining a connection path which can be connected by wire bondingfrom the connection relationship between said internal circuits and saidexternals and the positions of said conductive pads; and (b)calculating, with respect to said connection path, the position of saidwire bond island provided on said first semiconductor chip.
 18. A methodfor designing semiconductor device which comprises a first semiconductorchip that includes a first internal circuit, at least one firstconductive pad which is provided on its upper surface and is connectedto said first internal circuit and at least one wire bond island servingas a conductive pad which is provided on its upper surface and is notconnected to said first internal circuit; and a second semiconductorchip provided on said first semiconductor chip that includes a secondinternal circuit and a second conductive pad which is provided on itsupper surface and is connected to said second internal circuit, whereinsaid at least one first conductive pad is connected to said secondconductive pad, and said at least one first conductive pad is connectedto externals, said method comprising the steps of: (a) determiningwhether or not at least one connection path determined from theconnection relationship between said internal circuits and saidexternals and the positions of said at least one first conductive padand said second conductive pad can be connected by wire bonding; (b)calculating the position of said at least one wire bond island providedon said first semiconductor chip if it is determined in said step (a)that said at least one connection path can be connected by wire bonding;and (c) if it is determined in said step (a) that said connection pathcannot be connected by wire bonding, calculating the position of said atleast one wire bond island provided on said first semiconductor chip andthen changing the configuration of said at least one wire bond island sothat said connection path can be connected by wire bonding.
 19. Themethod for designing semiconductor device of claim 18, wherein aplurality of said at least one first conductive pads are provided, saidplurality of at least one connection paths are determined in said step(a), a plurality of the positions of said at least one wire bond islandsare obtained in said step (b) or (c), said method further comprising thestep of: (d) with respect to two of said plurality of connection paths,changing the positions of the wire bond islands so that the distancesbetween said first conductive pads and said wire bond islands are equal.20. A method for designing semiconductor device which comprises a firstsemiconductor chip that includes a first internal circuit and a firstconductive pad which is provided on its upper surface and is connectedto said first internal circuit; and a second semiconductor chip providedon said first semiconductor chip that includes a second internal circuitand a second conductive pad which is provided on its upper surface andis connected to said second internal circuit, wherein said firstconductive pad is connected to said second conductive pad, and saidfirst conductive pad is connected to externals, said method comprisingthe steps of: (a) determining a connection path from the connectionrelationship between the internal circuits and said externals and thepositions of the conductive pads; (b) when said connection path isconnected by a connecting member, determining whether or not a delayvalue of said connection path is within a tolerance; and (c) if it isdetermined in said step (b) that the delay value of said connection pathis not within a tolerance, changing the connecting member so that thedelay value of said connection path is within a tolerance.
 21. Themethod for designing semiconductor device of claim 20, wherein in saidstep (c), materials for said connecting member are changed so that thedelay value of said connection path is within a tolerance.
 22. Themethod for designing semiconductor device of claim 20, wherein in saidstep (c), the number of wires structuring said connecting member ischanged so that the delay value of said connection path is within atolerance.
 23. A method for designing semiconductor device whichcomprises a first semiconductor chip and a second semiconductor chipprovided on said first semiconductor chip, comprising the steps of: (a)determining the area on said first semiconductor chip that said secondsemiconductor chip is to be disposed from the arrangement relationshipbetween said first semiconductor chip and said second semiconductor chipand configurations of said first semiconductor chip and secondsemiconductor chip; and (b) in order to form a first convex portion withwhich said second semiconductor chip engages, determining thearrangement of said first convex portion on said first semiconductorchip and the configuration of said first convex portion.
 24. The methodfor designing semiconductor device of claim 23 further comprising thestep of: (c) in order to form a second convex portion on which saidsecond semiconductor chip can slide, determining the arrangement of saidsecond convex portion on said first semiconductor chip and theconfiguration of said second convex portion.
 25. A method for designingsemiconductor device which comprises a first semiconductor chip and atleast one second semiconductor chip provided on said first semiconductorchip, comprising the steps of: (a) determining the area on said firstsemiconductor chip that said at least one second semiconductor chip isto be disposed from the arrangement relationship between said firstsemiconductor chip and said at least one second semiconductor chip andconfigurations of said first semiconductor chip and said at least onesecond semiconductor chip; (b) detecting the number of said at least onesecond semiconductor chips; (c) if the number of said at least onesecond semiconductor chips is 1 in said step (b), determining thepositions of a first engagement portion on said first semiconductor chipand a second engagement portion on said second semiconductor chip whichis fitted into said first engagement portion and the configurations ofsaid first engagement portion and said second engagement portion; and(d) if the number of said at least one second semiconductor chips is aplural number in said step (b), determining the positions of said firstengagement portions on said first semiconductor chip and said secondengagement portions on said second semiconductor chips fitted into saidfirst engagement portions and the configurations of said firstengagement portions and said second engagement portions.
 26. A methodfor designing semiconductor device which comprises a first semiconductorchip and at least one second semiconductor chip provided on said firstsemiconductor chip, comprising the steps of: (a) determining the area onsaid first semiconductor chip that said at least one secondsemiconductor chip is to be disposed from the arrangement relationshipbetween said first semiconductor chip and said at least one secondsemiconductor chip and the configurations of said first semiconductorchip and said at least one second semiconductor chip; (b) detecting thenumber of said at least one second semiconductor chips; (c) if thenumber of said at least one second semiconductor chips is I in said step(b), determining the configuration of a mark indicating the position onsaid first semiconductor chip that said second semiconductor chip is tobe provided; and (d) if the number of said at least one secondsemiconductor chips is a plural number in said step (b), determining theconfiguration of marks indicating the positions on said firstsemiconductor chip that said second semiconductor chips are to beprovided.
 27. A method for designing semiconductor device whichcomprises an internal circuit, comprising the step of determining, froma netlist and the configuration of semiconductor chip, the positions ofwire bonding pad provided on said semiconductor chip and connected tosaid internal circuit and bump connection pad connected to said internalcircuit in parallel with said wire bonding pad.
 28. A method fordesigning semiconductor device which comprises a first semiconductorchip that includes a first internal circuit and a plurality of firstconductive pad provided on its upper surface; and a second semiconductorchip provided on said first semiconductor chip that includes a secondinternal circuit and a plurality of conductive pads provided on it uppersurface, wherein said first conductive pads are connected to said secondconductive pads, and a ground potential is supplied to at least one ofsaid plurality of first conductive pads, said method comprising the stepof selecting a first conductive pad and a second conductive pad with aground potential being applied thereto from the connection relationshipbetween the internal circuits and the positions of the conductive pads.29. A computer readable recording medium incorporated into a computerused for designing a semiconductor device which comprises a firstsemiconductor chip that includes a first internal circuit, a firstconductive pad which is provided on its upper surface and is connectedto said first internal circuit and a wire bond island serving as aconductive pad which is provided on its upper surface and is notconnected to said first internal circuit and a second semiconductor chipprovided on said first semiconductor chip which includes a secondinternal circuit and a second conductive pad which is provided on itsupper surface and is connected to said second internal circuit, whereinsaid first conductive pad is connected to said second conductive pad andsaid first conductive pad is connected to externals, recorded in saidrecording medium is the program for a computer to perform the steps of:(a) determining a connection path which can be connected by wire bondingfrom the connection relationship between said internal circuits and saidexternals and the positions of said conductive pads; and (b)calculating, with respect to said connection path, the position of saidwire bond island provided on said first semiconductor chip.
 30. Acomputer readable recording medium incorporated into a computer used fordesigning a semiconductor device which comprises a first semiconductorchip that includes a first internal circuit, at least one firstconductive pad which is provided on it upper surface and is connected tosaid first internal circuit and at least one wire bond island serving asa conductive pad which is provided on its upper surface and is notconnected to said first internal circuit and a second semiconductor chipprovided on said first semiconductor chip that includes a secondinternal circuit and a second conductive pad which is provided on itsupper surface and is connected to said second internal circuit, whereinsaid at least one first conductive pad is connected to said secondconductive pad, and said at least one first conductive pad is connectedto externals, recorded in said recording medium is the program for acomputer to perform the steps of: (a) determining whether or not atleast one connection path determined from the connection relationshipbetween said internal circuits and said externals and the positions ofsaid at least one first conductive pad and said second conductive padcan be connected by wire bonding; (b) if it is determined in said step(a) that said at least one connection path can be connected by wirebonding, calculating the position of said at least one wire bond islandprovided on said first semiconductor chip; and (c) if it is determinedin said step (a) that said connection path cannot be connected by wirebonding, calculating the position of said at least one wire bond islandprovided on said first semiconductor chip and then changing theconfiguration of said at least one wire bond island so that saidconnection path can be connected by wire bonding.
 31. A computerreadable recording medium incorporated into a computer used fordesigning a semiconductor device which comprises a first semiconductorchip that includes a first internal circuit and a first conductive padwhich is provided on it upper surface and is connected to said firstinternal circuit and a second semiconductor chip provided on said firstsemiconductor chip that includes a second internal circuit and a secondconductive pad which is provided on its upper surface and is connectedto said second internal circuit, wherein said first conductive pad isconnected to said second conductive pad and said first conductive pad isconnected to externals, recorded in said recording medium is the programfor a computer to perform the steps of: (a) determining a connectionpath from the connection relationship between said internal circuits andsaid externals and the positions of said conductive pads; (b) when saidconnection path is connected by a connecting member, determining whetheror not a delay value of said connection path is within a tolerance; and(c) if it is determined in said step (b) that the delay value of saidconnection path is not within a tolerance, changing the connectingmember so that the delay of said connection path is within a tolerance.32. A computer readable recording medium incorporated into a computerused for designing a semiconductor device which comprises a firstsemiconductor chip and a second semiconductor chip provided on saidfirst semiconductor chip, recorded in said recording medium is theprogram for a computer to perform the steps of: (a) determining the areaon said first semiconductor chip that said second semiconductor chip isto be mounted from the arrangement relationship between said firstsemiconductor chip and said second semiconductor chip and theconfigurations of said first semiconductor chip and said secondsemiconductor chip; and (b) determining the arrangement of a firstconvex portion on said first semiconductor chip and the configuration ofthe first convex portion in order to form the first convex portion saidsecond semiconductor chip engages with.
 33. A computer readablerecording medium incorporated into a computer used for designing asemiconductor device which comprises a first semiconductor chip and atleast one second semiconductor chip provided on said first semiconductorchip, recorded in said recording medium is the program for a computer toperform the steps of: (a) determining the area on said firstsemiconductor chip that said at least one second semiconductor chip isto be disposed from the arrangement relationship between said firstsemiconductor chip and said at least one second semiconductor chip andthe configurations of said first semiconductor chip and said at leastone second semiconductor chip; (b) detecting the number of said at leastone second semiconductor chips; (c) if the number of said at least onesecond semiconductor chips is 1 in said step (b), determining thepositions of a first engagement portion on said first semiconductor chipand a second engagement portion on said second semiconductor chip fittedinto said first engagement portion and the configurations of said firstengagement portion and said second engagement portion; and (d) if thenumber of said at least one second semiconductor chips is a pluralnumber in said step (b), determining the positions of said firstengagement portions on said first semiconductor chip and said secondengagement portions on said second semiconductor chips fitted into saidfirst engagement portions and the configurations of said firstengagement portions and said second engagement portions.
 34. A computerreadable recording medium incorporated into a computer used fordesigning a semiconductor device which comprises a first semiconductorchip and at least one second semiconductor chip provided on said firstsemiconductor chip, recorded in said recording medium is the program fora computer to perform the steps of: (a) determining the area on saidfirst semiconductor chip that said at least one second semiconductorchip is to be disposed from the arrangement relationship between saidfirst semiconductor chip and said at least one second semiconductor chipand the configurations of said first semiconductor chip and said atleast one second semiconductor chip; (b) detecting the number of said atleast one second semiconductor chips; (c) if the number of said at leastone second semiconductor chips is 1 in said step (b), determining theconfiguration of a mark indicating the position on said firstsemiconductor chip that said second semiconductor chip is to beprovided; and (d) if the number of said at least one secondsemiconductor chips is a plural number in said step (b), determining theconfiguration of marks indicating the positions on said firstsemiconductor chip that said second semiconductor chips are to beprovided.
 35. A computer readable recording medium incorporated into acomputer used for designing a semiconductor device with an internalcircuit, recorded in said recording medium is the program for a computerto perform the step of determining, from a netlist and the configurationof a semiconductor chip, the positions of wire bonding pad provided onsaid semiconductor chip and connected to said internal circuit and bumpconnection pad connected to said internal circuit in parallel with saidwire bonding pad.
 36. A computer readable recording medium incorporatedinto a computer used for designing a semiconductor device whichcomprises a first semiconductor chip that includes a first internalcircuit and a plurality of first conductive pads provided on its uppersurface and a second semiconductor chip provided on said firstsemiconductor chip that includes a second internal circuit and aplurality of second conductive pads provided on its upper surface,wherein said first conductive pads are connected to said secondconductive pads and a ground potential is supplied to at least one ofsaid plurality of first conductive pads, recorded in said recordingmedium is the program for a computer to perform the step of selecting afirst conductive pad and a second conductive pad with the groundpotential being applied thereto from the connection relationship betweensaid internal circuits and the positions of said conductive pads.